US5502674A
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Method and apparatus for repair of memory by redundancy
Assignee: Sharp Corp
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Filing: 1994-04-06
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Granted: 1996-03-26
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Expires: 2014-04-06
Abstract
Abstract A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.
Inventors
- 👤 Michael J. Griffus
- 👤 Robert G. Pollachek
- 👤 Giao N. Pham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:23
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/814; G11C29/816; G11C29/82; G11C29/83; G11C29/832
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
73 words
For a memory device having plural memory blocks each for storing data and each including a data-carrying bitline that is normally coupled by a bitline-loading means to a power line, a method comprising the steps of: (a) designating one or more memory blocks of the memory device as being defective or otherwise non-operational; and (b) in response to said designation, decoupling the corresponding bitline of the designated memory block from the power line.
Claim 2
Dependent Claim
73 words
For a memory device having plural memory blocks each for storing data and each including a data-carrying bitline that is normally coupled by a bitline-loading means to a power line, a method comprising the steps of: (a) designating one or more memory blocks of the memory device as being defective or otherwise non-operational; and (b) in response to said designation, decoupling the corresponding bitline of the designated memory block from the power line.
Claim 3
Dependent Claim
37 words
A method according to claim 1 further comprising the step of: (c) activating a normally-nonoperational, redundant memory block to function in place of one of the memory blocks that has been designated as defective or otherwise non-operational.
Claim 4
Independent Claim
230 words
A method for producing a plurality of integrated circuits each containing a memory device, the memory device of each produced integrated circuit having one or more memory blocks for storing data and a corresponding one or more bitlines operatively coupled to the memory blocks for carrying the data, the bitlines of operational memory blocks being normally biased to a reference voltage when data is read from the memory device, said method comprising the steps of: (a) providing a plurality of switchable coupling means on each integrated circuit for selectively coupling or decoupling corresponding ones of the bitlines to a reference voltage source in response to a respective plurality of switch command signals supplied to the switchable coupling means; (b) providing a plurality of programmable designating means on each integrated circuit for selectively designating each memory block of the integrated circuit as being operational or non-operational, the programmable designating means being operatively coupled to control the switch command signals and cause the switchable coupling means of memory blocks designated as non-operational to decouple their respective bitlines from the reference voltage source; (c) testing the memory blocks of each integrated circuit for conformance to a prespecified set of performance criteria; and (d) programming the designating means of each integrated circuit to designate as non-operational, one or more memory blocks of the integrated circuit that is found during said testing to be nonconforming.
Claim 5
Independent Claim
230 words
A method for producing a plurality of integrated circuits each containing a memory device, the memory device of each produced integrated circuit having one or more memory blocks for storing data and a corresponding one or more bitlines operatively coupled to the memory blocks for carrying the data, the bitlines of operational memory blocks being normally biased to a reference voltage when data is read from the memory device, said method comprising the steps of: (a) providing a plurality of switchable coupling means on each integrated circuit for selectively coupling or decoupling corresponding ones of the bitlines to a reference voltage source in response to a respective plurality of switch command signals supplied to the switchable coupling means; (b) providing a plurality of programmable designating means on each integrated circuit for selectively designating each memory block of the integrated circuit as being operational or non-operational, the programmable designating means being operatively coupled to control the switch command signals and cause the switchable coupling means of memory blocks designated as non-operational to decouple their respective bitlines from the reference voltage source; (c) testing the memory blocks of each integrated circuit for conformance to a prespecified set of performance criteria; and (d) programming the designating means of each integrated circuit to designate as non-operational, one or more memory blocks of the integrated circuit that is found during said testing to be nonconforming.
Claim 6
Dependent Claim
177 words
A method according to claim 1 including the steps of: defining said memory device on an integrated circuit; providing a plurality of switchable coupling means on the integrated circuit for selectively coupling or decoupling corresponding ones of the bitlines to the reference voltage source in response to a respective plurality of switch command signals supplied to the switchable coupling means; providing a plurality of programmable designating means on the integrated circuit for selectively designating each memory block of the integrated circuit as being operational or non-operational; testing the memory blocks of the integrated circuit for conformance to a prespecified set of performance criteria; programming the designating means of the integrated circuit to designate as non-operational, one or more memory blocks of the integrated circuit that is found during said testing to be nonconforming; and in response to said programming, setting the corresponding switch command signals of those memory blocks that are designated as non-operational, so as to switch the corresponding switchable coupling means into nonconductive states and thereby decouple the corresponding bitlines from the reference voltage source.
Claim 7
Dependent Claim
25 words
A method according to claim 4 wherein said step of programming the designating means includes using a laser beam to cut open a column-kill fuse.
Claim 8
Dependent Claim
50 words
A method according to claim 4 wherein each said memory block includes a word line and wherein said step of testing the memory blocks includes detecting undesired current leakage between the word line of a given memory block and the reference voltage source that renders the given memory block non-operational.
Claim 9
Dependent Claim
51 words
A method according to claim 4 wherein said step of testing the memory blocks includes detecting undesired current leakage between the bitline of a given memory block and a second reference voltage source complementary to the first relative reference voltage source, the undesired current leakage rendering the given memory block non-operational.
Claim 10
Dependent Claim
68 words
A method according to claim 4 wherein each said memory block includes a pass transistor having a gate and a source, the source being connected to the corresponding bitline, and wherein said step of testing the memory blocks includes detecting undesired current leakage between the pass transistor gate of a given memory block and the pass transistor source, said undesired current leakage rendering the given memory block non-operational.
Claim 11
Dependent Claim
68 words
A method according to claim 4 wherein each said memory block includes a pass transistor having a source and a drain, the source being connected to the corresponding bitline, and wherein said step of testing the memory blocks includes detecting undesired current leakage between the pass transistor source of a given memory block and the pass transistor drain, said undesired current leakage rendering the given memory block non-operational.
Claim 12
Dependent Claim
19 words
A method according to claim 1 wherein each said memory block includes a plurality of repeatedly reprogrammable memory cells.
Claim 13
Dependent Claim
19 words
A method according to claim 3 wherein each said memory block includes a plurality of repeatedly reprogrammable memory cells.
Claim 14
Dependent Claim
130 words
For a memory device having plural memory blocks, wherein each of the plural memory blocks is for storing a plurality of data bits, wherein each memory block includes one or more data-carrying bitlines for conducting one or more data bits during a memory read operation, and wherein each bitline is normally coupled by a bitline-loading means to a reference voltage source at least during the memory read operation, a method comprising the steps of: (a) designating one or more memory blocks of the memory device as being defective or otherwise non-operational; and (b) in response to said designation, decoupling a corresponding one or more bitlines of each designated memory block from the reference voltage source in order to inhibit excess current draw by the designated one or more memory blocks.
Claim 15
Dependent Claim
130 words
For a memory device having plural memory blocks, wherein each of the plural memory blocks is for storing a plurality of data bits, wherein each memory block includes one or more data-carrying bitlines for conducting one or more data bits during a memory read operation, and wherein each bitline is normally coupled by a bitline-loading means to a reference voltage source at least during the memory read operation, a method comprising the steps of: (a) designating one or more memory blocks of the memory device as being defective or otherwise non-operational; and (b) in response to said designation, decoupling a corresponding one or more bitlines of each designated memory block from the reference voltage source in order to inhibit excess current draw by the designated one or more memory blocks.
Claim 16
Dependent Claim
44 words
A method according to claim 12 wherein each memory block includes at least two data-carrying bitlines and said decoupling step includes: (b.1) in response to said designation, decoupling the corresponding, at least two bitlines of each designated memory block from the reference voltage source.
Claim 17
Dependent Claim
17 words
A method according to claim 12 wherein said designating step includes: (a.1) programing a nonvolatile indicating means.
Claim 18
Dependent Claim
39 words
A method according to claim 14 wherein the nonvolatile indicating means includes a programmable means that is programmed by said programing step and is selected from the group consisting of: a fuse, an antifuse, and a floating gate transistor.
Claim 19
Dependent Claim
14 words
A method according to claim 14 wherein the programming step includes using a laser.
Claim 20
Dependent Claim
108 words
A method according to claim 12 wherein: said memory device includes one or more word lines each extending across a plurality of said memory blocks such that an undesirable current conducting path may form between one or more of the word lines and one or more of the bitlines of the memory blocks across which the one or more word lines extend; and said step of decoupling is such that it inhibits a flow of current from the reference voltage source through the undesirable current conducting path of a designated memory block in the case where the undesirable current conducting path is present in the designated memory block.
Claim 21
Dependent Claim
91 words
A method according to claim 12 wherein: said memory device includes ground means extending across at least one of said memory blocks such that an undesirable current conducting path may form between the ground means and a bitline of the at least one memory block; and said step of decoupling is such that it inhibits a flow of current from the reference voltage source through the undesirable current conducting path of a designated memory block in the case where the undesirable current conducting path is present in the designated memory block.
Claim 22
Dependent Claim
19 words
A method according to claim 12 wherein each said memory block includes a plurality of repeatedly reprogrammable memory cells.
Claim 23
Dependent Claim
25 words
A method according to claim 19 wherein at least one of said repeatedly reprogrammable memory cells is a static random access memory cell (SRAM cell).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-26 | 1999-09-25 | 2000-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-26 | 2003-09-25 | 2004-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-26 | 2007-09-25 | 2008-03-26 | $7700.00 | Window Closed / Lapsed |