US5502668A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device capable of low-voltage programming
Assignee: Rohm Co Ltd
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Filing: 1994-02-25
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Granted: 1996-03-26
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Expires: 2014-02-25
Abstract
Abstract A poly-silicon or amorphous silicon plate having cone-like protrusions is provided on a Si substrate in a tunnel window area such that the edges of the protrusions are placed very close to a floating gate. Alternatively, the top surface of a Si substrate is shaped into protrusions.
Inventors
- 👤 Noriyuki Shimoji
- 👤 Hidemi Takasu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:10
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/50; H10D62/57; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
85 words
An FET memory comprising: a silicon substrate; a floating gate; a tunnel insulating layer provided between the floating gate and a diffusion region of the silicon substrate on a data line side; and a silicon plate provided on the silicon substrate and having a plurality of adjacent asperities extending into the tunnel insulating layer to produce a localized increase in electric field strength within the tunnel insulating layer, the asperities being placed close to the floating gate to enhance electron injection into the floating gate.
Claim 2
Dependent Claim
85 words
An FET memory comprising: a silicon substrate; a floating gate; a tunnel insulating layer provided between the floating gate and a diffusion region of the silicon substrate on a data line side; and a silicon plate provided on the silicon substrate and having a plurality of adjacent asperities extending into the tunnel insulating layer to produce a localized increase in electric field strength within the tunnel insulating layer, the asperities being placed close to the floating gate to enhance electron injection into the floating gate.
Claim 3
Dependent Claim
14 words
The FET memory of claim 1, wherein the silicon plate is made of poly-silicon.
Claim 4
Dependent Claim
15 words
The FET memory of claim 1, wherein the silicon plate is made of amorphous silicon.
Claim 5
Dependent Claim
14 words
The FET memory of claim 1, wherein each asperity includes at least one protrusion.
Claim 6
Dependent Claim
30 words
The FET memory of claim 1, wherein the silicon plate is disposed in a window formed by removing a part of a gate oxide film formed on the silicon substrate.
Claim 7
Dependent Claim
16 words
The FET memory of claim 1, wherein the FET memory is an electrically erasable programmable ROM.
Claim 8
Dependent Claim
90 words
An FET memory comprising: a silicon substrate; a floating gate; an insulating layer having a tunnel window provided between the floating gate and a diffusion region of the silicon substrate on a data line side; and a surface of the silicon substrate in the diffusion region being formed with a plurality of adjacent asperities to produce a localized increase in electric field strength within the tunnel window, the asperities being placed close to the floating gate and extending into the tunnel window to enhance electron injection into the floating gate.
Claim 9
Dependent Claim
90 words
An FET memory comprising: a silicon substrate; a floating gate; an insulating layer having a tunnel window provided between the floating gate and a diffusion region of the silicon substrate on a data line side; and a surface of the silicon substrate in the diffusion region being formed with a plurality of adjacent asperities to produce a localized increase in electric field strength within the tunnel window, the asperities being placed close to the floating gate and extending into the tunnel window to enhance electron injection into the floating gate.
Claim 10
Dependent Claim
14 words
The FET memory of claim 7, wherein each asperity includes at least one protrusion.
Claim 11
Dependent Claim
16 words
The FET memory of claim 7, wherein the FET memory is an electrically erasable programmable ROM.
References Cited (Backward Citations)
US5017979A
Cited
US5063423A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-26 | 1999-09-25 | 2000-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-26 | 2003-09-25 | 2004-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-26 | 2007-09-25 | 2008-03-26 | $7700.00 | Window Closed / Lapsed |