Circuit and method of bit-packing and bit-unpacking using a barrel shifter

Claim 2

A translator circuit for packing variable length input data into fixed length output data, comprising: circuit means for converting a first control signal to a width signal indicating number of bits of width of said first control signal; an accumulator having an input coupled for receiving said width signal and having an output for providing a select signal; a decoder having a control input coupled for receiving said select signal for selecting one of a plurality of outputs of said decoder; and a barrel shifter receiving variable length input data and further receiving control signals from said plurality of outputs of said decoder for translating said variable length input data to a plurality of outputs according to said control signals, said barrel shifter including, (a) a plurality of first conductors, (b) a plurality of second conductors, (c) a first transistor having a gate, a drain and a source, said gate being coupled for receiving a first one of said control signals, said drain being coupled to a first one of said plurality of first conductors, said source being coupled to a first one of said plurality of second conductors, (d) a second transistor having a gate, a drain and a source, said gate being coupled for receiving a second one of said control signals, said drain being coupled to said first one of said plurality of first conductors, said source being coupled to a second one of said plurality of second conductors, (e) a third transistor having a gate, a drain and a source, said gate being coupled for receiving said second one of said control signals, said drain being coupled to a second one of said plurality of first conductors, said source being coupled to said first one of said plurality of second conductors, and (f) a data storage circuit having first and second inputs and respective first and second outputs coupled to first and second ones of said outputs of said barrel shifter, said first input being coupled to said first one of said plurality of second conductors for latching data at said first output, said second input being coupled to said second one of said plurality of second conductors for latching data at said second output.

Claim 3

The translator circuit of claim 1 further comprising a register having a plurality of inputs coupled for receiving said plurality of outputs from said barrel shifter and having an output for providing the fixed length output data.

Claim 4

The translator circuit of claim 1 wherein said data storage circuit includes: a first inverter having an input coupled to said first one of said plurality of second conductors and having an output; a second inverter having an input coupled to said output of said first inverter and having an output coupled to said first one of said outputs of said barrel shifter; and a fourth transistor having a gate, a drain and a source, said gate being coupled for receiving a clock signal, said drain being coupled to said output of said second inverter, said source being coupled to said input of said first inverter.

Claim 5

The translator circuit of claim 3 wherein said data storage circuit includes: a third inverter having an input coupled to said second one of said plurality of second conductors and having an output; a fourth inverter having an input coupled to said output of said third inverter and having an output coupled to said second one of said outputs of said barrel shifter; and a fifth transistor having a gate, a drain and a source, said gate being coupled for receiving said clock signal, said drain being coupled to said output of said fourth inverter, said source being coupled to said input of said third inverter.

Claim 6

The translator circuit of claim 1 wherein said barrel shifter further includes; fourth transistor having a gate, a drain and a source, said gate being coupled for receiving a third one of said control signals, said drain being coupled to said first one of said plurality of first conductors, said source being coupled to a third one of said plurality of second conductors; a fifth transistor having a gate, a drain and a source, said gate being coupled for receiving said third one of said control signals, said drain being coupled to said second one of said plurality of first conductors, said source being coupled to said second one of said plurality of second conductors; a sixth transistor having a gate, a drain and a source, said gate being coupled for receiving said third one of said control signals, said drain being coupled to a third one of said plurality of first conductors, said source being coupled to said first one of said plurality of second conductors; a seventh transistor having a gate, a drain and a source, said gate being coupled for receiving a fourth one of said control signals, said drain being coupled to said second one of said plurality of first conductors, said source being coupled to said third one of said plurality of second conductors; an eighth transistor having a gate, a drain and a source, said gate being coupled for receiving said fourth one of said control signals, said drain being coupled to said third one of said plurality of first conductors, said source being coupled to said second one of said plurality of second conductors; and a ninth transistor having a gate, a drain and a source, said gate being coupled for receiving a fifth one of said control signals, said drain being coupled to said third one of said plurality of first conductors, said source being coupled to said third one of said plurality of second conductors.

Claim 7

The translator circuit of claim 5 wherein said data storage circuit further includes: a first inverter having an input coupled to said third one of said plurality of second conductors and having an output; a second inverter having an input coupled to said output of said first inverter and having an output coupled to a third one of said outputs of said barrel shifter; and a tenth transistor having a gate, a drain and a source, said gate being coupled for receiving a clock signal, said drain being coupled to said output of said second inverter, said source being coupled to said input of said first inverter.

Claim 8

A translator circuit coupled for receiving variable length input data and further coupled for receiving control signals for translating said variable length input data to fixed length output data at a plurality of outputs according to said control signals, comprising: a plurality of first conductors; a plurality of second conductors; a first transistor having a gate, a drain and a source, said gate being coupled for receiving a first one of said control signals, said drain being coupled to a first one of said plurality of first conductors, said source being coupled to a first one of said plurality of second conductors; a second transistor having a gate, a drain and a source, said gate being coupled for receiving a second one of said control signals, said drain being coupled to said first one of said plurality of first conductors, said source being coupled to a second one of said plurality of second conductors; a third transistor having a gate, a drain and a source, said gate being coupled for receiving said second one of said control signals, said drain being coupled to a second one of said plurality of first conductors, said source being coupled to said first one of said plurality of second conductors; and a data storage circuit having first and second inputs and respective first and second outputs coupled to first and second ones of said outputs of said barrel shifter, said first input being coupled to said first one of said plurality of second conductors for latching data at said first output, said second input being coupled to said second one of said plurality of second conductors for latching data at said second output.

Claim 9

A translator circuit coupled for receiving variable length input data and further coupled for receiving control signals for translating said variable length input data to fixed length output data at a plurality of outputs according to said control signals, comprising: a plurality of first conductors; a plurality of second conductors; a first transistor having a gate, a drain and a source, said gate being coupled for receiving a first one of said control signals, said drain being coupled to a first one of said plurality of first conductors, said source being coupled to a first one of said plurality of second conductors; a second transistor having a gate, a drain and a source, said gate being coupled for receiving a second one of said control signals, said drain being coupled to said first one of said plurality of first conductors, said source being coupled to a second one of said plurality of second conductors; a third transistor having a gate, a drain and a source, said gate being coupled for receiving said second one of said control signals, said drain being coupled to a second one of said plurality of first conductors, said source being coupled to said first one of said plurality of second conductors; and a data storage circuit having first and second inputs and respective first and second outputs coupled to first and second ones of said outputs of said barrel shifter, said first input being coupled to said first one of said plurality of second conductors for latching data at said first output, said second input being coupled to said second one of said plurality of second conductors for latching data at said second output.

Claim 10

The translator circuit of claim 7 wherein said data storage circuit includes: a first inverter having an input coupled to said first one of said plurality of second conductors and having an output; a second inverter having an input coupled to said output of said first inverter and having an output coupled to said first one of said outputs of said barrel shifter; and a fourth transistor having a gate, a drain and a source, said gate being coupled for receiving a clock signal, said drain being coupled to said output of said second inverter, said source being coupled to said input of said first inverter.

Claim 11

The translator circuit of claim 8 wherein said data storage circuit further includes: a third inverter having an input coupled to said second one of said plurality of second conductors and having an output; a fourth inverter having an input coupled to said output of said third inverter and having an output coupled to said second one of said outputs of said barrel shifter; and a fifth transistor having a gate, a drain and a source, said gate being coupled for receiving said clock signal, said drain being coupled to said output of said fourth inverter, said source being coupled to said input of said third inverter.

Claim 12

The translator circuit of claim 9 wherein said barrel shifter further includes: a fourth transistor having a gate, a drain and a source, said gate being coupled for receiving a third one of said control signals, said drain being coupled to said first one of said plurality of first conductors, said source being coupled to a third one of said plurality of second conductors; a fifth transistor having a gate, a drain and a source, said gate being coupled for receiving said third one of said control signals, said drain being coupled to said second one of said plurality of first conductors, said source being coupled to said second one of said plurality of second conductors; and a sixth transistor having a gate, a drain and a source, said gate being coupled for receiving said third one of said control signals, said drain being coupled to a third one of said plurality of first conductors, said source being coupled to said first one of said plurality of second conductors.

Claim 13

The translator circuit of claim 10 wherein said barrel shifter further includes: a seventh transistor having a gate, a drain and a source, said gate being coupled for receiving a fourth one of said control signals, said drain being coupled to said second one of said plurality of first conductors, said source being coupled to said third one of said plurality of second conductors; an eighth transistor having a gate, a drain and a source, said gate being coupled for receiving said fourth one of said control signals, said drain being coupled to said third one of said plurality of first conductors, said source being coupled to said second one of said plurality of second conductors; and a ninth transistor having a gate, a drain and a source, said gate being coupled for receiving a fifth one of said control signals, said drain being coupled to said third one of said plurality of first conductors, said source being coupled to said third one of said plurality of second conductors.

Claim 14

The translator circuit of claim 11 wherein said data storage circuit further includes: a first inverter having an input coupled to said third one of said plurality of second conductors and having an output; a second inverter having an input coupled to said output of said first inverter and having an output coupled to a third one of said outputs of said barrel shifter; and a tenth transistor having a gate, a drain and a source, said gate being coupled for receiving a clock signal, said drain being coupled to said output of said second inverter, said source being coupled to said input of said first inverter.

Claim 15

In a data compression chip, a translator circuit for packing variable length input data into fixed length output data, comprising: an accumulator having an input coupled for receiving a width signal and having an output for providing a select signal; a decoder having a control input coupled for receiving said select signal for selecting one of a plurality of outputs of said decoder; and a barrel shifter receiving variable length input data and further receiving control signals from said plurality of outputs of said decoder for translating said variable length input data to a plurality of outputs according to said control signals, said barrel shifter including, (a) a plurality of first conductors, (b) a plurality of second conductors, (c) a first transistor having a gate, a drain and a source, said gate being coupled for receiving a first one of said control signals, said drain being coupled to a first one of said plurality of first conductors, said source being coupled to a first one of said plurality of second conductors, (d) a second transistor having a gate, a drain and a source, said gate being coupled for receiving a second one of said control signals, said drain being coupled to said first one of said plurality of first conductors, said source being coupled to a second one of said plurality of second conductors, (e) a third transistor having a gate, a drain and a source, said gate being coupled for receiving said second one of said control signals, said drain being coupled to a second one of said plurality of first conductors, said source being coupled to said first one of said plurality of second conductors, and (f) a data storage circuit having first and second inputs and respective first and second outputs coupled to first and second ones of said outputs of said barrel shifter, said first input being coupled to said first one of said plurality of second conductors for latching data at said first output, said second input being coupled to said second one of said plurality of second conductors for latching data at said second output.

Claim 16

In a data compression chip, a translator circuit for packing variable length input data into fixed length output data, comprising: an accumulator having an input coupled for receiving a width signal and having an output for providing a select signal; a decoder having a control input coupled for receiving said select signal for selecting one of a plurality of outputs of said decoder; and a barrel shifter receiving variable length input data and further receiving control signals from said plurality of outputs of said decoder for translating said variable length input data to a plurality of outputs according to said control signals, said barrel shifter including, (a) a plurality of first conductors, (b) a plurality of second conductors, (c) a first transistor having a gate, a drain and a source, said gate being coupled for receiving a first one of said control signals, said drain being coupled to a first one of said plurality of first conductors, said source being coupled to a first one of said plurality of second conductors, (d) a second transistor having a gate, a drain and a source, said gate being coupled for receiving a second one of said control signals, said drain being coupled to said first one of said plurality of first conductors, said source being coupled to a second one of said plurality of second conductors, (e) a third transistor having a gate, a drain and a source, said gate being coupled for receiving said second one of said control signals, said drain being coupled to a second one of said plurality of first conductors, said source being coupled to said first one of said plurality of second conductors, and (f) a data storage circuit having first and second inputs and respective first and second outputs coupled to first and second ones of said outputs of said barrel shifter, said first input being coupled to said first one of said plurality of second conductors for latching data at said first output, said second input being coupled to said second one of said plurality of second conductors for latching data at said second output.

Claim 17

The translator circuit of claim 13 further comprising a register having a plurality of inputs coupled for receiving said plurality of outputs from said barrel shifter and having an output for providing the fixed length output data.

Claim 18

The translator circuit of claim 13 wherein said data storage circuit includes: a first inverter having an input coupled to said first one of said plurality of second conductors and having an output; a second inverter having an input coupled to said output of said first inverter and having an output coupled to said first one of said outputs of said barrel shifter; a fourth transistor having a gate, a drain and a source, said gate being coupled for receiving a clock signal, said drain being coupled to said output of said second inverter, said source being coupled to said input of said first inverter; a third inverter having an input coupled to said second one of said plurality of second conductors and having an output; a fourth inverter having an input coupled to said output of said third inverter and having an output coupled to said second one of said outputs of said barrel shifter; and a fifth transistor having a gate, a drain and a source, said gate being coupled for receiving said clock signal, said drain being coupled to said output of said fourth inverter, said source being coupled to said input of said third inverter.

Claim 19

The translator circuit of claim 19 wherein said barrel shifter further includes: a fourth transistor having a gate, a drain and a source, said gate being coupled for receiving a third one of said control signals, said drain being coupled to said first one of said plurality of first conductors, said source being coupled to a third one of said plurality of second conductors; a fifth transistor having a gate, a drain and a source, said gate being coupled for receiving said third one of said control signals, said drain being coupled to said second one of said plurality of first conductors, said source being coupled to said second one of said plurality of second conductors; a sixth transistor having a gate, a drain and a source, said gate being coupled for receiving said third one of said control signals, said drain being coupled to a third one of said plurality of first conductors, said source being coupled to said first one of said plurality of second conductors; a seventh transistor having a gate, a drain and a source, said gate being coupled for receiving a fourth one of said control signals, said drain being coupled to said second one of said plurality of first conductors, said source being coupled to said third one of said plurality of second conductors; an eighth transistor having a gate, a drain and a source, said gate being coupled for receiving said fourth one of said control signals, said drain being coupled to said third one of said plurality of first conductors, said source being coupled to said second one of said plurality of second conductors; a ninth transistor having a gate, a drain and a source, said gate being coupled for receiving a fifth one of said control signals, said drain being coupled to said third one of said plurality of first conductors, said source being coupled to said third one of said plurality of second conductors; a first inverter having an input coupled to said third one of said plurality of second conductors and having an output; a second inverter having an input coupled to said output of said first inverter and having an output coupled to a third one of said outputs of said barrel shifter; and a tenth transistor having a gate, a drain and a source, said gate being coupled for receiving a clock signal, said drain being coupled to said output of said second inverter, said source being coupled to said input of said first inverter.

Claim 20

In a data compression chip, a translator circuit coupled for receiving variable length input data and further coupled for receiving control signals for translating said variable length input data to fixed length output data at a plurality of outputs according to the control signals, the translator circuit comprising: a plurality of first conductors coupled for receiving the variable length input data; a plurality of second conductors; a transistor array having a plurality of first conduction terminals coupled to said plurality of first conductors, a plurality of second conduction terminals coupled to said plurality of second conductors, and a plurality of control terminals coupled for receiving the control signals for translating the variable length input data to the fixed length output data in response to a selected one of the control signals while other ones of the control signals are deselected; and a data storage circuit having a first input coupled to a first one of said plurality of second conductors for latching a first bit of the fixed length output data at a first output, and having a second input coupled to a second one of said plurality of second conductors for latching a second bit of the fixed length output data at a second output when said other ones of plurality of control signals are deselected.

Claim 21

In a data compression chip, a translator circuit coupled for receiving variable length input data and further coupled for receiving control signals for translating said variable length input data to fixed length output data at a plurality of outputs according to the control signals, the translator circuit comprising: a plurality of first conductors coupled for receiving the variable length input data; a plurality of second conductors; a transistor array having a plurality of first conduction terminals coupled to said plurality of first conductors, a plurality of second conduction terminals coupled to said plurality of second conductors, and a plurality of control terminals coupled for receiving the control signals for translating the variable length input data to the fixed length output data in response to a selected one of the control signals while other ones of the control signals are deselected; and a data storage circuit having a first input coupled to a first one of said plurality of second conductors for latching a first bit of the fixed length output data at a first output, and having a second input coupled to a second one of said plurality of second conductors for latching a second bit of the fixed length output data at a second output when said other ones of plurality of control signals are deselected.

Claim 22

The translator circuit of claim 17 wherein said transistor array includes: a first transistor having a gate, a drain and a source, said gate being coupled for receiving a first one of said control signals, said drain being coupled to a first one of said plurality of first conductors, said source being coupled to a first one of said plurality of second conductors; a second transistor having a gate, a drain and a source, said gate being coupled for receiving a second one of said control signals, said drain being coupled to said first one of said plurality of first conductors, said source being coupled to a second one of said plurality of second conductors; and a third transistor having a gate, a drain and a source, said gate being coupled for receiving said second one of said control signals, said drain being coupled to a second one of said plurality of first conductors, said source being coupled to said first one of said plurality of second conductors.

Claim 23

The translator circuit of claim 18 wherein said data storage circuit includes: a first inverter having an input coupled to said first one of said plurality of second conductors and having an output; a second inverter having an input coupled to said output of said first inverter and having an output coupled to said first one of said outputs of said barrel shifter; a fourth transistor having a gate, a drain and a source, said gate being coupled for receiving a clock signal, said drain being coupled to said output of said second inverter, said source being coupled to said input of said first inverter; a third inverter having an input coupled to said second one of said plurality of second conductors and having an output; a fourth inverter having an input coupled to said output of said third inverter and having an output coupled to said second one of said outputs of said barrel shifter; and a fifth transistor having a gate, a drain and a source, said gate being coupled for receiving said clock signal, said drain being coupled to said output of said fourth inverter, said source being coupled to said input of said third inverter.

Claim 24

The translator circuit of claim 18 wherein said barrel shifter further includes: a fourth transistor having a gate, a drain and a source, said gate being coupled for receiving a third one of said control signals, said drain being coupled to said first one of said plurality of first conductors, said source being coupled to a third one of said plurality of second conductors; a fifth transistor having a gate, a drain and a source, said gate being coupled for receiving said third one of said control signals, said drain being coupled to said second one of said plurality of first conductors, said source being coupled to said second one of said plurality of second conductors; and a sixth transistor having a gate, a drain and a source, said gate being coupled for receiving said third one of said control signals, said drain being coupled to a third one of said plurality of first conductors, said source being coupled to said first one of said plurality of second conductors; a seventh transistor having a gate, a drain and a source, said gate being coupled for receiving a fourth one of said control signals, said drain being coupled to said second one of said plurality of first conductors, said source being coupled to said third one of said plurality of second conductors; an eighth transistor having a gate, a drain and a source, said gate being coupled for receiving said fourth one of said control signals, said drain being coupled to said third one of said plurality of first conductors, said source being coupled to said second one of said plurality of second conductors; and a ninth transistor having a gate, a drain and a source, said gate being coupled for receiving a fifth one of said control signals, said drain being coupled to said third one of said plurality of first conductors, said source being coupled to said third one of said plurality of second conductors.

Claim 25

The translator circuit of claim 20 wherein said data storage circuit further includes: a first inverter having an input coupled to said third one of said plurality of second conductors and having an output; a second inverter having an input coupled to said output of said first inverter and having an output coupled to a third one of said outputs of said barrel shifter; and a tenth transistor having a gate, a drain and a source, said gate being coupled for receiving a clock signal, said drain being coupled to said output of said second inverter, said source being coupled to said input of said first inverter.