Large capacity modular ATM switch

Claim 2

A large capacity modular ATM switch for exchanging data in ATM cells among I/O ports, comprising: a plurality of switching modules arranged in a logical m×n matrix, m and n being positive integers, each switching module having an I/O port, a buffer, bus selector means and a control circuit; H data buses separately connecting modules in each separate row of the matrix to send data to all the modules in each row; V data buses separately connecting modules in each separate column of the matrix to send data to all the modules in each column; H and V control buses connecting modules in rows and columns to exchange control signals among the module control circuits; the bus selector means of each module connected to the H and V data buses for selectively receiving data therefrom in response to the control signals on the H and V control buses; the buffer connected to both data buses for storing one or more ATM cells in transit between the I/O ports; and the control circuits for generating the control signals in response to the state of the buffer.

Claim 3

The high capacity modular ATM switch according to claim 1, in which there are any number less than or equal to m×n switch modules in the matrix.

Claim 4

The high capacity ATM switch according to claim 2, in which the control signals comprise a connection request and a connection grant, and the data are exchanged in a train of a variable number of ATM cells among switch modules in response to the connection request and connection grant.

Claim 5

A large capacity modular ATM switch for exchanging data in ATM cells among I/O ports comprising: a plurality of switching modules arranged in a logical m×n matrix, m and n being positive integers, each switching module having an I/O port, an input and output buffer and an intermediate buffer, H and V bus selector means and a control circuit; H data buses, each H data bus connecting modules in each row of the matrix to send data to all the modules in the row; V data buses, each V data bus connecting modules in each column of the matrix to send data to all the modules in the column; H control buses, each H control bus connecting modules in each row of the matrix; V control buses, each V control bus connecting modules in each column of the matrix; each of the H and V bus selector means of each module connected to respective H and V data buses for receiving data therefrom in response to control signals on the respective control buses; the intermediate buffer connecting respectively between the V bus selector means and H data bus; the input buffer of each module sending data to the V data bus, the output buffer of each module receiving data from the H bus selector means which is connected to the H data buses; and the control circuits for generating the control signals in response to the state of the buffers.

Claim 6

A large capacity modular ATM switch for exchanging data in ATM cells among I/O ports comprising: a plurality of switching modules arranged in a logical m×n matrix, m and n being positive integers, each switching module having an I/O port, an input and output buffer and an intermediate buffer, H and V bus selector means and a control circuit; H data buses, each H data bus connecting modules in each row of the matrix to send data to all the modules in the row; V data buses, each V data bus connecting modules in each column of the matrix to send data to all the modules in the column; H control buses, each H control bus connecting modules in each row of the matrix; V control buses, each V control bus connecting modules in each column of the matrix; each of the H and V bus selector means of each module connected to respective H and V data buses for receiving data therefrom in response to control signals on the respective control buses; the intermediate buffer connecting respectively between the V bus selector means and H data bus; the input buffer of each module sending data to the V data bus, the output buffer of each module receiving data from the H bus selector means which is connected to the H data buses; and the control circuits for generating the control signals in response to the state of the buffers.

Claim 7

The high capacity ATM switch according to claim 4, in which there are any number less than or equal to m×n switch modules in the matrix.

Claim 8

The high capacity ATM switch according to claim 5, in which the input buffer, output buffer and intermediate buffers are portions of a single memory; and each H and V data bus comprises a plurality of data bus lines in that each buffer drives one of the plurality of bus lines, the bus selector means is connected to all the bus lines but only selects one bus line from which it receives data in response to the control signal.

Claim 9

The high capacity ATM switch according to claim 6, in which V and H data buses comprise fiber optics, optical splitters and fiber optic shuffle boxes connecting the fiber optics and optical splitters.

Claim 10

The high capacity ATM switch according to claim 7, in which the control signals comprise a connection request and a connection grant, and the data are exchanged in a train of a variable number of ATM cells among I/O ports in response to the connection request and connection grant.

Claim 11

The high capacity ATM switch according to claim 6, in which V and H data buses comprise fiber optics for carrying wavelength division multiplexed beams, wavelength selective filters, and fiber optic shuffle boxes connecting the fiber optics and the wavelength selective filters.

Claim 12

A large capacity modular ATM switch for exchanging data in ATM cells among I/O ports comprising: a plurality of switching modules arranged in a logical m×n matrix, m and n being positive integers, each switching module having an I/O port, a buffer, bus selector means and a control circuit; H data buses separately connecting modules in each separate row of the matrix to send data to all the modules in each row; V and W data buses, each separately connecting modules in each separate column of the matrix to send data to all the modules in each column; H, V and W control buses connecting modules in rows and columns to exchange control signals among the module control circuits; the bus selector means of each module connected to H, V and W data buses for selectively receiving data therefrom in response to the control signals on the H, V and W control buses; the buffer connected to one of the data buses for storing one or more ATM cells in transit between the I/O ports; and the control circuits for generating the control signals in response to the state of the buffer.

Claim 13

A large capacity modular ATM switch for exchanging data in ATM cells among I/O ports comprising: a plurality of switching modules arranged in a logical m×n matrix, m and n being positive integers, each switching module having an I/O port, a buffer, bus selector means and a control circuit; H data buses separately connecting modules in each separate row of the matrix to send data to all the modules in each row; V and W data buses, each separately connecting modules in each separate column of the matrix to send data to all the modules in each column; H, V and W control buses connecting modules in rows and columns to exchange control signals among the module control circuits; the bus selector means of each module connected to H, V and W data buses for selectively receiving data therefrom in response to the control signals on the H, V and W control buses; the buffer connected to one of the data buses for storing one or more ATM cells in transit between the I/O ports; and the control circuits for generating the control signals in response to the state of the buffer.

Claim 14

The high capacity ATM switch according to claim 10, in which there are any number less than or equal to m×n switch modules in the matrix.

Claim 15

The high capacity ATM switch according to claim 11, in which the control signals comprise a connection request and a connection grant, and the data are exchanged in a train of a variable number of ATM cells among I/O ports in response to the connection request and connection grant.

Claim 16

A large capacity modular ATM switch for exchanging data in ATM cells among I/O ports comprising: a plurality of switching modules arranged in a logical m×n matrix, m and n being positive integers, each switching module having an I/O port, an input and output buffer and intermediate buffers, H, V and W bus selector means and a control circuit; H data buses, each H data bus connecting modules in each row of the matrix to send data to all the modules in the row; V and W data buses, each V or W data bus connecting modules in each column of the matrix to send data to all the modules in the column; H control buses, each H control bus connecting modules in each row of the matrix; V and W control buses, each V or W control bus connecting modules in each column of the matrix; each of the H, V and W bus selector means of each module connected to respective H, V and W data buses for receiving data therefrom in response to control signals on the respective control buses; the intermediate buffers connecting between the V bus selector means and H data buses and between the H bus selector means and W data buses; the input buffer of each module sending data to the V data buses, the output buffer of each module receiving data from the H bus selector means which is connected to the H data buses; and the control circuits for generating the control signals in response to the state of the buffer.

Claim 17

A large capacity modular ATM switch for exchanging data in ATM cells among I/O ports comprising: a plurality of switching modules arranged in a logical m×n matrix, m and n being positive integers, each switching module having an I/O port, an input and output buffer and intermediate buffers, H, V and W bus selector means and a control circuit; H data buses, each H data bus connecting modules in each row of the matrix to send data to all the modules in the row; V and W data buses, each V or W data bus connecting modules in each column of the matrix to send data to all the modules in the column; H control buses, each H control bus connecting modules in each row of the matrix; V and W control buses, each V or W control bus connecting modules in each column of the matrix; each of the H, V and W bus selector means of each module connected to respective H, V and W data buses for receiving data therefrom in response to control signals on the respective control buses; the intermediate buffers connecting between the V bus selector means and H data buses and between the H bus selector means and W data buses; the input buffer of each module sending data to the V data buses, the output buffer of each module receiving data from the H bus selector means which is connected to the H data buses; and the control circuits for generating the control signals in response to the state of the buffer.

Claim 18

The high capacity ATM switch according to claim 13, in which there are any number less than or equal to m×n switch modules in the matrix.

Claim 19

The high capacity ATM switch according to claim 14, in which the input buffer, output buffer and intermediate buffers are portions of a single memory; and each H, V and W data buses comprises a plurality of data bus lines in that each buffer drives one of the plurality of bus lines, the bus selector means monitors all the bus lines but only selects one bus line from which it receives data in response to the control signal.

Claim 20

The high capacity ATM switch according to claim 15, in which V, H and W data buses comprise fiber optics, optical splitters and fiber optic shuffle boxes connecting the fiber optics and optical splitters.

Claim 21

The high capacity ATM switch according to claim 16, in which a multiplexer and demultiplexer are connected to the single memory, the V data buses are faster in speed than the H data buses and function as the V and W data buses in cooperation with the multiplexer and demultiplexer.

Claim 22

The high capacity ATM switch according to claim 17, in which the control signals comprise a connection request and a connection grant, and the data are exchanged in a train of a variable number of ATM cells among I/O ports in response to the connection request and connection grant.

Claim 23

The high capacity ATM switch according to claim 15, in which a multiplexer and demultiplexer are connected to the single memory, the V data buses are faster in speed than the H data buses and function as the V and W data buses in cooperation with the multiplexer and demultiplexer.

Claim 24

The high capacity ATM switch according to claim 19, in which the control signals comprise a connection request and a connection grant, and the data are exchanged in a train of a variable number of ATM cells among I/O ports in response to the connection request and connection grant.

Claim 25

The high capacity ATM switch according to claim 15, in which V, H and W data buses comprise fiber optics for carrying wavelength division multiplexed beams, wavelength selective filters, and fiber optic shuffle boxes connecting the fiber optics and the wavelength selective filters.