Vector data buffer and method of reading data items from a banked storage without changing the data sequence thereof

Claim 3

A vector data buffer device which receives a plurality of arrayed data items fetched from a storage, said storage including a plurality of independently operating storage banks and said storage having stored therein the plurality of arrayed data items, comprising: a vector data buffer which stores therein said arrayed data items fetched from said storage, said vector data buffer includes a plurality of bank memories in a predetermined number, said predetermined number being determined based on a combination of a number of said storage banks, a data width of each of said independently operating storage banks and a data width of each of said plurality of arrayed data items; switch means for connecting individual bank memories of said plurality of bank memories of said vector data buffer to respective ones of said independently operating storage banks; switch control means for dynamically changing connection relationships of said switch means on the basis of, at least, a storage address and data intervals of said plurality of arrayed data items wherein any one of said plurality of bank memories which receives data items from one of said plurality of storage banks may not receive data items from another of said plurality of storage banks during processing of a request for fetching said plurality of arrayed data items; and storing address generation means for generating entry addresses within said plurality of bank memories in which said plurality of arrayed data items fetched are to be stored.

Claim 4

A vector data buffer device which receives a plurality of arrayed data items fetched from a storage, said storage including a plurality of independently operating storage banks and said storage having stored therein the plurality of arrayed data items, comprising: a vector data buffer which stores therein said arrayed data items fetched from said storage, said vector data buffer includes a plurality of bank memories in a predetermined number, said predetermined number being determined based on a combination of a number of said storage banks, a data width of each of said independently operating storage banks and a data width of each of said plurality of arrayed data items; switch means for connecting individual bank memories of said plurality of bank memories of said vector data buffer to respective ones of said independently operating storage banks; switch control means for dynamically changing connection relationships of said switch means on the basis of, at least, a storage address and data intervals of said plurality of arrayed data items wherein any one of said plurality of bank memories which receives data items from one of said plurality of storage banks may not receive data items from another of said plurality of storage banks during processing of a request for fetching said plurality of arrayed data items; and storing address generation means for generating entry addresses within said plurality of bank memories in which said plurality of arrayed data items fetched are to be stored.

Claim 5

A vector data buffer device according to claim 2, wherein the predetermined number of said plurality of bank memories of said vector data buffer is set to be n (integer) times larger than said number of said storage banks, while data width of each of said storage banks is set to be n times larger than the data width of each of said plurality of bank memories, and n bank memories of said plurality of bank memories are simultaneously connected to a corresponding one of said independently operating storage banks.

Claim 6

A vector data processor comprising: a main storage which includes a plurality of independently operating storage banks; a vector data buffer device for receiving a plurality of arrayed data items fetched from said main storage, including: a vector data buffer which stores therein said plurality of arrayed data items fetched from said main storage, said vector data buffer includes a plurality of bank memories in a predetermined number, said predetermined number being determined based on a combination of a number of said independently operating storage banks, a data width of each of said storage banks and the data width of each of said plurality of arrayed data items, switch means for connecting the individual bank memories of said plurality of bank memories of said vector data buffer to any of said storage banks, switch control means for dynamically changing connection relationships of said switch means on the basis of, at least, a storage address and data intervals of said plurality of arrayed data items wherein any one of said plurality of bank memories which receives data items from one of said plurality of storage banks may not receive data items from another of said plurality of storage banks during processing of a request for fetching said plurality of arrayed data items, and storing address generation means for generating address information items which indicate the bank memories of said data buffer for storing said arrayed data items which are fetched from the individual storing banks, as well as entry addresses within said plurality of bank memories in which said plurality of arrayed data items fetched are to be stored; arithmetic means for successively deriving and processing said plurality of arrayed data items stored in said vector data buffer device; and a vector register for storing a processed result of said arithmetic means therein.

Claim 7

A vector data processor comprising: a main storage which includes a plurality of independently operating storage banks; a vector data buffer device for receiving a plurality of arrayed data items fetched from said main storage, including: a vector data buffer which stores therein said plurality of arrayed data items fetched from said main storage, said vector data buffer includes a plurality of bank memories in a predetermined number, said predetermined number being determined based on a combination of a number of said independently operating storage banks, a data width of each of said storage banks and the data width of each of said plurality of arrayed data items, switch means for connecting the individual bank memories of said plurality of bank memories of said vector data buffer to any of said storage banks, switch control means for dynamically changing connection relationships of said switch means on the basis of, at least, a storage address and data intervals of said plurality of arrayed data items wherein any one of said plurality of bank memories which receives data items from one of said plurality of storage banks may not receive data items from another of said plurality of storage banks during processing of a request for fetching said plurality of arrayed data items, and storing address generation means for generating address information items which indicate the bank memories of said data buffer for storing said arrayed data items which are fetched from the individual storing banks, as well as entry addresses within said plurality of bank memories in which said plurality of arrayed data items fetched are to be stored; arithmetic means for successively deriving and processing said plurality of arrayed data items stored in said vector data buffer device; and a vector register for storing a processed result of said arithmetic means therein.

Claim 8

A vector data processor according to claim 4, wherein said vector data buffer device serves also as said vector register.