Highly producible magnetoresistive RAM process

Claim 2

A process for forming a magnetoresistive memory on a semiconductor substrate having an underlying integrated circuit component and an insulating layer formed thereover, and forming an interconnecting between said device and said underlying component, comprising the steps of: forming a first insulating layer on said substrate; forming a materials stack on said first insulating layer; forming a first amorphous dielectric layer on said materials stack; selectively removing portions of said first amorphous dielectric layer to define a pattern for a magnetic bit; removing portions of said materials stack and said first insulating layer according to said pattern to define a magnetic bit having a bit edge profile and having a bit end located over said underlying component; forming a second amorphous dielectric layer over said first amorphous dielectric layer; removing portions of said second amorphous dielectric layer to expose said bit end with a remaining portion of said second amorphous dielectric layer protecting said bit edge profile; selectively forming a via in said insulating substrate at said bit end to expose a portion of said underlying component; forming a first conductive layer over said second amorphous dielectric layer, said first conductive layer contacting said bit end and extending into said via and contacting said component; and etching said first conductive layer to form said interconnection.

Claim 3

A process as recited in claim 1 wherein said first amorphous dielectric layer and said second amorphous dielectric layer comprise bias sputter quartz.

Claim 4

A process as recited in claim 1 wherein said first amorphous dielectric layer and said second amorphous dielectric layer comprise sputter silicon nitride.

Claim 5

A process as recited in claim 2 wherein said process of removing portions of said magnetic materials layer and said first insulating layer according to said pattern to define a magnetic bit having a bit edge profile and having a bit end located over said underlying component comprises ion milling.

Claim 6

A process as recited in claim 2 wherein said step of removing portions of said second bias sputter quartz layer to expose said bit end comprises removing a portion of said first bias sputter quartz layer at said bit end to provide an improved first metal step coverage.

Claim 7

A process as recited in claim 5 wherein said step of removing portions of said first and second bias sputter quartz layers to expose said bit end further comprises selectively removing portions of said first and second bias sputter quartz layers at a location for a shorting bar, said location spaced from said bit end.

Claim 8

A process as recited in claim 6 wherein said step of forming a materials stack is done by successive sputter deposition steps.

Claim 9

A process for forming a magnetoresistive memory device on a semiconductor substrate having an insulating layer formed thereover and an underlying integrated circuit component, and forming an interconnection between said device and said underlying component, comprising the steps of: forming a stack of a plurality of materials on said insulating layer, said stack including a first layer of a magnetic material and a second layer of a magnetic material, said first and second layers separated by a third layer of material; forming a first layer of an amorphous dielectric on said stack; selectively removing portions of said first layer of said amorphous dielectric to define a pattern for a magnetic bit; removing portions of said stack according to said pattern to define a magnetic bit having a bit edge profile and having a bit end located over said underlying component; forming a second layer of an amorphous dielectric over said first layer of amorphous dielectric; removing portions of said second layer of amorphous dielectric to expose said bit end with a remaining portion of said second layer of amorphous dielectric protecting said bit edge profile; selectively forming a via in said insulating layer at said bit end to expose a portion of said underlying component; forming a first conductive layer over said second layer of amorphous dielectric, said first conductive layer extending into said via and contacting said component; and etching said first conductive layer to form said interconnection.

Claim 10

A process for forming a magnetoresistive memory device on a semiconductor substrate having an insulating layer formed thereover and an underlying integrated circuit component, and forming an interconnection between said device and said underlying component, comprising the steps of: forming a stack of a plurality of materials on said insulating layer, said stack including a first layer of a magnetic material and a second layer of a magnetic material, said first and second layers separated by a third layer of material; forming a first layer of an amorphous dielectric on said stack; selectively removing portions of said first layer of said amorphous dielectric to define a pattern for a magnetic bit; removing portions of said stack according to said pattern to define a magnetic bit having a bit edge profile and having a bit end located over said underlying component; forming a second layer of an amorphous dielectric over said first layer of amorphous dielectric; removing portions of said second layer of amorphous dielectric to expose said bit end with a remaining portion of said second layer of amorphous dielectric protecting said bit edge profile; selectively forming a via in said insulating layer at said bit end to expose a portion of said underlying component; forming a first conductive layer over said second layer of amorphous dielectric, said first conductive layer extending into said via and contacting said component; and etching said first conductive layer to form said interconnection.

Claim 11

A process as recited in claim 8 wherein said step of forming a stack of a plurality of materials on said insulating layer includes forming a diffusion barrier on said insulating layer before forming said stack.

Claim 12

A process as recited in claim 8 wherein said first layer of an amorphous dielectric and said second layer of an amorphous dielectric comprise bias sputter quartz.

Claim 13

A process as recited in claim 9 wherein said stack comprises a first layer of a NiFeCo alloy, a layer of tantalum nitride and a second layer of a NiFeCo alloy.

Claim 14

A process for forming a magnetoresistive memory device on a semiconductor substrate having an insulating layer formed thereover and an underlying integrated circuit component, and forming an interconnection between said device and said underlying component, comprising the steps of: forming a diffusion barrier on said insulating layer; forming a stack of a plurality of materials on said insulating layer, said stack including a first layer of a magnetic material, and a second layer of a magnetic material, said first and second layers separated by a third layer of material; forming a first layer of bias sputter quartz on said stack; selectively removing portions of said first layer of bias sputter quartz to define a pattern for a magnetic bit; removing portions of said stack according to said pattern to define a magnetic bit having a bit edge profile and having a bit end located over said underlying component; forming a second layer of bias sputter quartz over said first layer of bias sputter quartz; performing ion milling to remove portions of said second layer of bias sputter quartz to expose said bit end with a remaining portion of said second layer of bias sputter quartz protecting said bit edge profile; selectively forming a via in said insulating layer at said bit end to expose a portion of said underlying component; forming a first metal layer over said second layer of bias sputter quartz, said first metal layer contacting said bit end and extending into said via and contacting said component; and etching said first metal layer to form a connection at said bit end.

Claim 15

A process for forming a magnetoresistive memory device on a semiconductor substrate having an insulating layer formed thereover and an underlying integrated circuit component, and forming an interconnection between said device and said underlying component, comprising the steps of: forming a diffusion barrier on said insulating layer; forming a stack of a plurality of materials on said insulating layer, said stack including a first layer of a magnetic material, and a second layer of a magnetic material, said first and second layers separated by a third layer of material; forming a first layer of bias sputter quartz on said stack; selectively removing portions of said first layer of bias sputter quartz to define a pattern for a magnetic bit; removing portions of said stack according to said pattern to define a magnetic bit having a bit edge profile and having a bit end located over said underlying component; forming a second layer of bias sputter quartz over said first layer of bias sputter quartz; performing ion milling to remove portions of said second layer of bias sputter quartz to expose said bit end with a remaining portion of said second layer of bias sputter quartz protecting said bit edge profile; selectively forming a via in said insulating layer at said bit end to expose a portion of said underlying component; forming a first metal layer over said second layer of bias sputter quartz, said first metal layer contacting said bit end and extending into said via and contacting said component; and etching said first metal layer to form a connection at said bit end.

Claim 16

A process as recited in claim 12 wherein said conductive layer comprises a first layer of TiW and a second layer of AlCu.

Claim 17

A process as recited in claim 12 wherein said step of removing portions of said second bias sputter quartz layer to expose said bit end comprises removing a portion of said first bias sputter quartz layer at said bit end.

Claim 18

A process as recited in claim 12 wherein said step of removing portions of said first and second bias sputter quartz layers to expose said bit end further comprises selectively removing portions of said first and second bias sputter quartz layers at a location for a shorting bar, said location spaced from said bit end.