US5496758A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication process of a semiconductor memory device having a multiple well structure in a recessed substrate
Assignee: Fujitsu Semiconductor Ltd
•
Filing: 1994-12-14
•
Granted: 1996-03-05
•
Expires: 2014-12-14
Abstract
Abstract A method for fabricating a semiconductor memory device includes the steps of forming, in a semiconductor substrate of a first conductivity type, a well of a second opposite conductivity type by protecting the substrate surface except for a part where the well of the second conductivity type is to be formed, oxidizing the exposed surface of the semiconductor substrate while using the same mask pattern to form a thick oxide film on the surface of the well, and removing the thick oxide film by an etching process to form a recessed surface on the well.
Inventors
- 👤 Taiji Ema
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:50
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; Y; Y10; Y10S; Y10S438/00; Y10S438/965
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
203 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming, on a first region of a semiconductor substrate of a first conductivity type, a first well of a second, opposite conductivity type; a mask process for forming a mask pattern on a surface of said semiconductor substrate, such that a second region, which is included in said first region, is exposed; introducing an impurity element of said first conductivity type into the surface of said semiconductor substrate in correspondence to said second region while using said mask pattern as a mask; causing a diffusion of said impurity element in said semiconductor substrate to form a second well of said first conductivity type in said first well in correspondence to said second region; causing an oxidation of the surface of said semiconductor substrate while using said mask pattern as a mask, to form an oxide layer on said second well such that said oxide layer covers said second well; and removing said oxide layer to form a recessed surface on the surface of said semiconductor substrate in correspondence to said second region, such that said recessed surface has a level lower than a level of a surface of said first region.
Claim 2
Independent Claim
203 words
A method for fabricating a semiconductor memory device, comprising the steps of: forming, on a first region of a semiconductor substrate of a first conductivity type, a first well of a second, opposite conductivity type; a mask process for forming a mask pattern on a surface of said semiconductor substrate, such that a second region, which is included in said first region, is exposed; introducing an impurity element of said first conductivity type into the surface of said semiconductor substrate in correspondence to said second region while using said mask pattern as a mask; causing a diffusion of said impurity element in said semiconductor substrate to form a second well of said first conductivity type in said first well in correspondence to said second region; causing an oxidation of the surface of said semiconductor substrate while using said mask pattern as a mask, to form an oxide layer on said second well such that said oxide layer covers said second well; and removing said oxide layer to form a recessed surface on the surface of said semiconductor substrate in correspondence to said second region, such that said recessed surface has a level lower than a level of a surface of said first region.
Claim 3
Dependent Claim
21 words
A method as claimed in claim 1, wherein said step of diffusion and said step of oxidation are conducted substantially simultaneously.
Claim 4
Dependent Claim
68 words
A method as claimed in claim 1, wherein said method further includes the steps of forming a memory cell array on said second region by forming memory cell transistors and corresponding memory cell capacitors on said recessed surface; and providing a planarized insulator layer having a planarized surface on said semiconductor substrate such that said planarized insulator layer covers said memory cell transistors and said memory cell capacitors.
Claim 5
Dependent Claim
90 words
A method as claimed in claim 3, wherein said method further includes the steps of: forming a conductive region in said semiconductor substrate such that said conductive region extends from said recessed surface to a surface of said first region; providing a contact hole on said planarized insulator layer in correspondence to said first region such that said contact hole exposes said conductive region; and filling said contact hole by a conductive material to form an electrode such that said electrode establishes an electrical contact with said exposed conductive region.
Claim 6
Dependent Claim
86 words
A method as claimed in claim 1, wherein said step for forming said first well comprises the steps of: forming a second mask pattern on said semiconductor substrate in correspondence to a third region so as to expose said first region; introducing an impurity element of said second conductivity type into said semiconductor substrate in correspondence to said first region while using said second mask pattern as a mask; and causing a diffusion of said impurity element of said second conductivity type in said first region.
Claim 7
Dependent Claim
124 words
A method as claimed in claim 5, wherein said method further comprises the steps of: oxidizing said semiconductor substrate to form an oxide film while using said second mask pattern as a mask, such that said oxide film covers said first region of said semiconductor substrate; removing said second mask pattern from said third region; introducing a second impurity element of said first conductivity type into said third region while using said oxide film as a mask; and causing a diffusion of said second impurity element in said third region to form a third well; wherein said step of forming said oxide film that covers said first region is conducted substantially simultaneously to said process of causing the diffusion of said second impurity element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-05 | 1999-09-04 | 2000-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-05 | 2003-09-04 | 2004-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-05 | 2007-09-04 | 2008-03-05 | $7700.00 | Window Closed / Lapsed |