US5496745A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for making bipolar transistor having an enhanced trench isolation
Assignee: Electronics and Telecommunications Research Institute
•
Filing: 1994-12-19
•
Granted: 1996-03-05
•
Expires: 2014-12-19
Abstract
Abstract Disclosed is a fabrication of a bipolar transistor using an enhanced trench isolation so as to improve integration and performance thereof, comprising the steps of sequentially etching back portions corresponding to a trench using a trench forming mask to a predetermined depth of the buried collector to form the trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a second nitride layer; etching back layers formed on a portion of the first insulating layer to form an opening in the active region; forming a first side wall on both edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on both sides of the first side wall; and forming an emitter layer on the intrinsic base.
Inventors
- 👤 Byung-Ryul Ryum
- 👤 Tae-Hyeon Han
- 👤 Soo-Min Lee
- 👤 Deok-Ho Cho
- 👤 Seong-Hearn Lee
- 👤 Jin-Young Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 15:48
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D10/054; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/011; Y10S148/072
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
225 words
A method of making a bipolar transistor comprising the steps of: providing a buried collector; providing a collector above the buried collector; forming a silicon oxide layer above the buried collector; using a trench forming mask to form a trench to a predetermined depth of the buried collector; filling a first insulating layer into the trench; polishing the first insulating layer to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the first insulating layer and the silicon oxide layer; removing the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a polysilicon layer, a third insulating layer and a nitride layer; etching layers formed on a portion of the first insulating layer to form an opening defined by edges in the active region; forming a first side wall on the edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on the edges of the first side wall; and forming an emitter layer on the intrinsic base.
Claim 2
Independent Claim
225 words
A method of making a bipolar transistor comprising the steps of: providing a buried collector; providing a collector above the buried collector; forming a silicon oxide layer above the buried collector; using a trench forming mask to form a trench to a predetermined depth of the buried collector; filling a first insulating layer into the trench; polishing the first insulating layer to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the first insulating layer and the silicon oxide layer; removing the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a polysilicon layer, a third insulating layer and a nitride layer; etching layers formed on a portion of the first insulating layer to form an opening defined by edges in the active region; forming a first side wall on the edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on the edges of the first side wall; and forming an emitter layer on the intrinsic base.
Claim 3
Dependent Claim
58 words
The method according to claim 1, wherein the insulating layer has a thickness of from 300 to 500 Å, and the polysilicon layer has about 2000 Å in thickness, and wherein the thickness of the polysilicon layer and the nitride layer is determined depending on a polishing selection rate of the trench depth to the first insulating layer.
Claim 4
Dependent Claim
31 words
The method according to claim 1, wherein the first insulating layer is comprised of one of Si 3 N 4 , SiO 2 and a silica glass containing boron and phosphorous.
Claim 5
Dependent Claim
32 words
The method according to claim 1, wherein the emitter layer is comprised of a single-layer polysilicon layer doped with an impurity having high concentration of 1×10 20 cm 31 3 or more.
Claim 6
Dependent Claim
66 words
The method according to claim 1, wherein the emitter layer is comprised of a multi-layer structure, the multi-layer structure being comprised of a lower layer composed of a single crystal silicon of 10 18 cm -3 or less and an upper layer formed on the lower layer and comprised of a polysilicon doped with an impurity having high concentration of 1×10 20 cm -3 and more.
Claim 7
Independent Claim
305 words
A method for making a bipolar transistor comprising the steps of: injecting an impurity into a silicon substrate to form a conductive buried collector; forming a collector layer over the silicon substrate; sequentially forming a first insulating layer, a first polysilicon layer, a silicon oxide layer, a first nitride layer and a second polysilicon layer on the collector layer; defining active and inactive regions using a patterned photoresist layer formed on the second polysilicon layer; removing layers formed on the first polysilicon layer of the inactive region; forming a side wall nitride layer at both sides of the layers formed on the active region; depositing a second insulating layer thereon; removing the side wall nitride layer and performing an etching to form a trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a nitride layer; etching back layers formed on a portion of the first insulating layer to form an opening in the active region; forming a first side wall on both edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on both sides of the first side wall; and forming an emitter layer on the intrinsic base.
Claim 8
Independent Claim
305 words
A method for making a bipolar transistor comprising the steps of: injecting an impurity into a silicon substrate to form a conductive buried collector; forming a collector layer over the silicon substrate; sequentially forming a first insulating layer, a first polysilicon layer, a silicon oxide layer, a first nitride layer and a second polysilicon layer on the collector layer; defining active and inactive regions using a patterned photoresist layer formed on the second polysilicon layer; removing layers formed on the first polysilicon layer of the inactive region; forming a side wall nitride layer at both sides of the layers formed on the active region; depositing a second insulating layer thereon; removing the side wall nitride layer and performing an etching to form a trench; filling an isolation insulating layer into the trench; polishing the isolation insulating layer up to a surface of the silicon oxide layer; sequentially forming a second insulating layer on the isolating insulating layer and the silicon oxide layer; removing the first polysilicon layer and the first insulating layer formed on an inactive region other than an active region defined by the trench; thermal-oxidizing the collector layer formed on the inactive region to form a thermal oxide layer; removing the second insulating layer and sequentially forming a third polysilicon, a third insulating layer and a nitride layer; etching back layers formed on a portion of the first insulating layer to form an opening in the active region; forming a first side wall on both edges of the opening and removing the first insulating layer; forming an intrinsic base at a region where the first insulating layer is removed to electrically connect the intrinsic base with an extrinsic base in self-alignment; forming a second side wall on both sides of the first side wall; and forming an emitter layer on the intrinsic base.
Claim 9
Dependent Claim
31 words
The method according to claim 6, wherein the isolation insulating layer is comprised of one of Si 3 N 4 , a polyimide and a silica glass containing boron and phosphorous.
Claim 10
Dependent Claim
32 words
The method according to claim 6, wherein the emitter layer is comprised of a single-layer polysilicon layer doped with an impurity having high concentration of 1×10 20 cm 31 3 or more.
Claim 11
Dependent Claim
66 words
The method according to claim 6, wherein the emitter layer is comprised of a multi-layer structure, the multi-layer structure being comprised of a lower layer composed of a single crystal silicon of 10 18 cm -3 or less and an upper layer formed on the lower layer and comprised of a polysilicon doped with an impurity having high concentration of 1×10 20 cm -3 and more.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-05 | 1999-09-04 | 2000-03-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-05 | 2003-09-04 | 2004-03-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-05 | 2007-09-04 | 2008-03-05 | $7700.00 | Window Closed / Lapsed |