Switched capacitor circuit

Claim 2

A switched capacitor circuit comprising: a capacitor for storing electric charges; MOS switching means for discharging said electric charges, said MOS switching means having a predetermined gate width and including a plurality of MOS transistors connected in parallel with each other, each transistor having a specific gate width, wherein said predetermined gate width is divided among said specific gate widths of said plurality of MOS transistors such that a sum of said specific gate widths corresponds to said predetermined gate width; and timing generating means for cyclically generating a plurality of predetermined timing signals to turn on said plurality of MOS transistors one after another for increasing an on-state resistance of said MOS switching means at a transient period thereof when said MOS switching means is turned on, and to turn off said plurality of MOS transistors simultaneously when said MOS switching means is turned off.

Claim 3

A switched capacitor circuit according to claim 1, wherein each of said plurality of MOS transistors are complementary-type. MOS transistors.

Claim 4

A switched capacitor circuit according to claim 1, wherein each of said plurality of MOS transistors are N-type MOS transistors.

Claim 5

A switched capacitor circuit according to claim 1, wherein each of said plurality of MOS transistors are P-type MOS transistors.

Claim 6

A switched capacitor circuit according to claim 1, wherein said timing generating means is connected with gate electrodes of said MOS transistors so as to output said timing signals to said gate electrodes.

Claim 7

A switched capacitor circuit according to claim 5, wherein said timing generating means inputs a clock pulse therein, and outputs clock signals to said gate electrodes, at least one of said clock signals being delayed by a predetermined time to rise as compared with the others.

Claim 8

A switched capacitor circuit according to claim 1, wherein each of said gate widths of said MOS transistors are equal in size.

Claim 9

A switched capacitor circuit according to claim 1, wherein said capacitor, said MOS switch and said timing generating means are built in a monolithic integrated circuit.

Claim 10

A switched capacitor circuit comprising: a capacitor for storing electric charges; a charging circuit for charging said capacitor, said charging circuit including: a first MOS switch device, said first MOS switch device having a first predetermined gate width and including a plurality of MOS transistors, each transistor having a specific gate width, said transistor being connected in parallel with each other, wherein said predetermined gate width is divided among said specific gate widths of said plurality of MOS transistors such that a sum of said specific gate widths corresponds to said predetermined gate width; a discharging circuit for discharging said capacitor, said discharging circuit including: a second MOS switch device, said second MOS switch device having a second predetermined gate width and including a plurality of MOS transistors, each transistor having said specific gate width and connected in parallel with each other, wherein a number of said MOS transistors included in said second MOS switch device is the same as a number of said MOS transistors included in said first MOS switch device; and timing generating means for cyclically generating a plurality of predetermined timing signals to control said first MOS switch device for charging said capacitor so as to turn on said plurality of MOS transistors included in said first MOS switch device in a first sequential order and so as to turn off said plurality of MOS transistors included in said first MOS switch device simultaneously, and to control said second MOS switch device for discharging said capacitor so as to turn on said plurality of MOS transistors included in said second MOS switch device in a second sequential order and so as to turn off said plurality of MOS transistors included in said second MOS switch device simultaneously.

Claim 11

A switched capacitor circuit comprising: a capacitor for storing electric charges; a charging circuit for charging said capacitor, said charging circuit including: a first MOS switch device, said first MOS switch device having a first predetermined gate width and including a plurality of MOS transistors, each transistor having a specific gate width, said transistor being connected in parallel with each other, wherein said predetermined gate width is divided among said specific gate widths of said plurality of MOS transistors such that a sum of said specific gate widths corresponds to said predetermined gate width; a discharging circuit for discharging said capacitor, said discharging circuit including: a second MOS switch device, said second MOS switch device having a second predetermined gate width and including a plurality of MOS transistors, each transistor having said specific gate width and connected in parallel with each other, wherein a number of said MOS transistors included in said second MOS switch device is the same as a number of said MOS transistors included in said first MOS switch device; and timing generating means for cyclically generating a plurality of predetermined timing signals to control said first MOS switch device for charging said capacitor so as to turn on said plurality of MOS transistors included in said first MOS switch device in a first sequential order and so as to turn off said plurality of MOS transistors included in said first MOS switch device simultaneously, and to control said second MOS switch device for discharging said capacitor so as to turn on said plurality of MOS transistors included in said second MOS switch device in a second sequential order and so as to turn off said plurality of MOS transistors included in said second MOS switch device simultaneously.

Claim 12

A switched capacitor circuit according to claim 9, wherein each of said plurality of MOS transistors included in said first MOS switch device and said second MOS switch device are complementary type MOS transistors.

Claim 13

A switched capacitor according to claim 9, wherein gate widths of each said plurality of MOS transistors included in said first MOS switch device and said second MOS switch device have a same size.

Claim 14

A switch capacitor circuit according to claim 9, further comprising: an integrator connected to said discharging circuit, said integrator including an operational amplifier and a feedback impedance comprising another capacitor.

Claim 15

A switched capacitor circuit comprising: a capacitor; a charging circuit for charging said capacitor, said charging circuit including: a first MOS switch device including two complementary MOS transistors connected in parallel, and a second MOS switch device including two complementary MOS transistors connected in parallel; a discharging circuit for discharging said capacitor, said discharging circuit including: a third MOS switch device including two complementary MOS transistors connected in parallel, and a fourth MOS switch device including two complementary MOS transistors connected in parallel, wherein said complementary MOS transistor included in said first, second, third and fourth MOS switch devices have a same size gate width; and timing generating means for cyclically generating a plurality of predetermined timing signals to sequentially turn on said complementary MOS transistors included in said first and said second MOS switch devices for charging said capacitor, to turn off said complementary MOS transistors included in said first and said second MOS switch devices simultaneously, to turn on said complementary MOS transistors included in said third and fourth MOS switch devices for discharging said capacitor, to turn off said complementary MOS transistors included in said third and fourth MOS switch devices simultaneously.

Claim 16

A switched capacitor circuit comprising: a capacitor; a charging circuit for charging said capacitor, said charging circuit including: a first MOS switch device including two complementary MOS transistors connected in parallel, and a second MOS switch device including two complementary MOS transistors connected in parallel; a discharging circuit for discharging said capacitor, said discharging circuit including: a third MOS switch device including two complementary MOS transistors connected in parallel, and a fourth MOS switch device including two complementary MOS transistors connected in parallel, wherein said complementary MOS transistor included in said first, second, third and fourth MOS switch devices have a same size gate width; and timing generating means for cyclically generating a plurality of predetermined timing signals to sequentially turn on said complementary MOS transistors included in said first and said second MOS switch devices for charging said capacitor, to turn off said complementary MOS transistors included in said first and said second MOS switch devices simultaneously, to turn on said complementary MOS transistors included in said third and fourth MOS switch devices for discharging said capacitor, to turn off said complementary MOS transistors included in said third and fourth MOS switch devices simultaneously.

Claim 17

A switch capacitor circuit according to claim 13, further comprising: an integrator connected to said discharging circuit, said integrator including an operational amplifier and a feedback impedance comprising another capacitor.