Semiconductor crystalline laminate structure, forming method of the same, and semiconductor device employing the same

Claim 2

A semiconductor crystalline laminate structure comprising a first semiconductor layer consisting of a first alloyed semiconductor, a second semiconductor layer which has an energy gap wider than that of said first alloyed semiconductor and a lattice constant smaller than that of said first alloyed semiconductor and consists of one semiconductor selected from a group consisting of single-element semiconductor, compound semiconductor, and alloyed semiconductor, and a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of said first alloyed semiconductor and is formed between said first semiconductor layer and said second semiconductor layer and in contact with each of them, wherein a semiconductor having a largest lattice constant among semiconductors constituting said first alloyed semiconductor is included only in said first semiconductor layer and said third semiconductor layer among said first, second, and third semiconductor layers, and is a semiconductor containing In as a constituent element, and the In mole fraction of said third semiconductor layer is within a range from 0.15 to 0.3, so as to prevent segregation of In from the first semiconductor layer into the second semiconductor layer.

Claim 3

A semiconductor crystalline laminate structure according to claim 1, wherein said first semiconductor layer is an InGaAs layer, and said second semiconductor layer is an AlGaAs layer (Al mole fraction 0 included), and said third semiconductor layer is an InAlGaAs layer (Ga mole fraction 0 included).

Claim 4

A semiconductor device having a semiconductor crystalline laminate structure comprising a first semiconductor layer consisting of a first alloyed semiconductor, a second semiconductor layer which has an energy gap wider than that of said first alloyed semiconductor and a lattice constant smaller than that of said first alloyed semiconductor and consists of one semiconductor selected from a group consisting of single-element semiconductor, compound semiconductor, and alloyed semiconductor, and a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of said first alloyed semiconductor and is formed between said first semiconductor layer and said second semiconductor layer and in contact with each of them, wherein a semiconductor having a largest lattice constant among semiconductors constituting said first alloyed semiconductor is included only in said first semiconductor layer and said third semiconductor layer among said first, second, and third semiconductor layers, wherein said semiconductor having a largest lattice constant is a semiconductor containing In as a constituent element, wherein the In mole fraction of said third semiconductor layer is within a range from 0.15 to 0.3, and wherein said semiconductor device is an HEMT, said first semiconductor layer is a channel, said second semiconductor layer is a carrier supply layer, and said third semiconductor layer is a spacer, said device further comprising a gate electrode overlying said channel, and source and drain electrodes respectively at opposite sides of the gate electrode.

Claim 5

A semiconductor device having a semiconductor crystalline laminate structure comprising a first semiconductor layer consisting of a first alloyed semiconductor, a second semiconductor layer which has an energy gap wider than that of said first alloyed semiconductor and a lattice constant smaller than that of said first alloyed semiconductor and consists of one semiconductor selected from a group consisting of single-element semiconductor, compound semiconductor, and alloyed semiconductor, and a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of said first alloyed semiconductor and is formed between said first semiconductor layer and said second semiconductor layer and in contact with each of them, wherein a semiconductor having a largest lattice constant among semiconductors constituting said first alloyed semiconductor is included only in said first semiconductor layer and said third semiconductor layer among said first, second, and third semiconductor layers, wherein said semiconductor having a largest lattice constant is a semiconductor containing In as a constituent element, wherein the In mole fraction of said third semiconductor layer is within a range from 0.15 to 0.3, and wherein said semiconductor device is an HEMT, said first semiconductor layer is a channel, said second semiconductor layer is a carrier supply layer, and said third semiconductor layer is a spacer, said device further comprising a gate electrode overlying said channel, and source and drain electrodes respectively at opposite sides of the gate electrode.

Claim 6

A semiconductor device having a semiconductor crystalline laminate structure comprising a first semiconductor layer consisting of a first alloyed semiconductor, a second semiconductor layer which has an energy gap wider than that of said first alloyed semiconductor and a lattice constant smaller than that of said first alloyed semiconductor and consists of one semiconductor selected from a group consisting of single-element semiconductor, compound semiconductor, and alloyed semiconductor, and a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of said first alloyed semiconductor and is formed between said first semiconductor layer and said second semiconductor layer and in contact with each of them, wherein a semiconductor having a largest lattice constant among semiconductors constituting said first alloyed semiconductor is included only in said first semiconductor layer and said third semiconductor layer among said first, second, and third semiconductor layers, wherein said semiconductor having a largest lattice constant is a semiconductor containing In as a constituent element, wherein the In mole fraction of said third semiconductor layer is within a range from 0.15 to 0.3, and wherein said semiconductor device is a quantum well semiconductor laser having a quantum well consisting of a well layer and a barrier layer as active layers, said first semiconductor layer is said well layer, and said second semiconductor layer and said third semiconductor layer are said barrier layers, said quantum well semiconductor laser further comprising a first electrode and a second electrode respectively at opposed sides of the quantum well, so as to cause light emission from the active layers.

Claim 7

A semiconductor device having a semiconductor crystalline laminate structure comprising a first semiconductor layer consisting of a first alloyed semiconductor, a second semiconductor layer which has an energy gap wider than that of said first alloyed semiconductor and a lattice constant smaller than that of said first alloyed semiconductor and consists of one semiconductor selected from a group consisting of single-element semiconductor, compound semiconductor, and alloyed semiconductor, and a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of said first alloyed semiconductor and is formed between said first semiconductor layer and said second semiconductor layer and in contact with each of them, wherein a semiconductor having a largest lattice constant among semiconductors constituting said first alloyed semiconductor is included only in said first semiconductor layer and said third semiconductor layer among said first, second, and third semiconductor layers, wherein said semiconductor having a largest lattice constant is a semiconductor containing In as a constituent element, wherein the In mole fraction of said third semiconductor layer is within a range from 0.15 to 0.3, and wherein said semiconductor device is a quantum well semiconductor laser having a quantum well consisting of a well layer and a barrier layer as active layers, said first semiconductor layer is said well layer, and said second semiconductor layer and said third semiconductor layer are said barrier layers, said quantum well semiconductor laser further comprising a first electrode and a second electrode respectively at opposed sides of the quantum well, so as to cause light emission from the active layers.

Claim 8

A semiconductor device according to claim 3, wherein said first semiconductor layer is an InGaAs layer, said second semiconductor layer is an AlGaAs layer (Al mole fraction 0 included), and said third semiconductor layer is an InAlGaAs layer (Ga mole fraction 0 included).

Claim 9

A semiconductor device according to claim 4, wherein said first semiconductor layer is an InGaAs layer, said second semiconductor layer is an AlGaAs layer (Al mole fraction 0 included), and said third semiconductor layer is an InAlGaAs layer (Ga mole fraction 0 included).

Claim 10

A semiconductor device according to claim 4, wherein the device further includes cladding layers respectively at opposed sides of the quantum well, interposed between the quantum well and the first electrode, and between the quantum well and the second electrode.

Claim 11

A semiconductor device according to claim 7, wherein the device further includes optical waveguide layers respectively at opposed sides of the quantum well, interposed between the quantum well and respective cladding layers.

Claim 12

A semiconductor device having a semiconductor crystalline laminate structure comprising a first semiconductor layer consisting of a first alloyed semiconductor, a second semiconductor layer which has an energy gap wider than that of said first alloyed semiconductor and a lattice constant smaller than that of said first alloyed semiconductor and consists of one semiconductor selected from a group consisting of single-element semiconductor, compound semiconductor, and alloyed semiconductor, and a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of said first alloyed semiconductor and is formed between said first semiconductor layer and said second semiconductor layer and in contact with each of them, wherein a semiconductor having a largest lattice constant among semiconductors constituting said first alloyed semiconductor is included only in said first semiconductor layer and said third semiconductor layer among said first, second, and third semiconductor layers, wherein said semiconductor having a largest lattice constant is a semiconductor containing In as a constituent element, wherein the In mole fraction of said third semiconductor layer is within a range from 0.15 to 0.3, wherein said semiconductor device is an FET, and wherein said first semiconductor layer is a channel of said FET.

Claim 13

A semiconductor device having a semiconductor crystalline laminate structure comprising a first semiconductor layer consisting of a first alloyed semiconductor, a second semiconductor layer which has an energy gap wider than that of said first alloyed semiconductor and a lattice constant smaller than that of said first alloyed semiconductor and consists of one semiconductor selected from a group consisting of single-element semiconductor, compound semiconductor, and alloyed semiconductor, and a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of said first alloyed semiconductor and is formed between said first semiconductor layer and said second semiconductor layer and in contact with each of them, wherein a semiconductor having a largest lattice constant among semiconductors constituting said first alloyed semiconductor is included only in said first semiconductor layer and said third semiconductor layer among said first, second, and third semiconductor layers, wherein said semiconductor having a largest lattice constant is a semiconductor containing In as a constituent element, wherein the In mole fraction of said third semiconductor layer is within a range from 0.15 to 0.3, wherein said semiconductor device is an FET, and wherein said first semiconductor layer is a channel of said FET.

Claim 14

A semiconductor device according to claim 9, wherein said first semiconductor layer is an InGaAs layer, said second semiconductor layer is an AlGaAs layer (Al mole fraction 0 included), and said third semiconductor layer is an InAlGaAs layer (Ga mole fraction 0 included).