US5493666A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory architecture using page mode writes and single level write buffering
Assignee: Apple Inc
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Filing: 1995-01-11
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Granted: 1996-02-20
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Expires: 2015-01-11
Abstract
Abstract A memory architecture including a memory cache which uses a single level of write buffering in combination with page mode writes to attain zero wait state operation for most memory accesses by a microprocessor. By the use of such a memory architecture, the speed advantages of more expensive buffering schemes, such as FIFO buffering, are obtained using less complex designs. The memory architecture utilizes same page detection logic and latching circuitry and takes advantage of a feature built into industry standard dynamic RAMs, namely page mode writes, to perform writes to memory which allow the processor to be freed before the write is completed for the most frequently occurring type of write operations.
Inventors
- 👤 Jonathan M. Fitch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:04
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0882
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
216 words
A memory system having an address bus and a data bus coupled to a dynamic random access memory array, a memory cache coupled to said address bus and said data bus, a tag array coupled to said address bus and a memory controller coupled to a central processing unit and said dynamic random access memory array, said memory system comprising: a) page mode write control means coupled to said address bus and said memory controller for controlling writes of data on said data bus to said dynamic random access memory array which are within a predetermined memory page; b) same page detection logic means for determining whether consecutive writes of data on said data bus to said dynamic random access memory array are within said predetermined memory page and generating a latch control signal for latching data on said data bus; c) latch means coupled to said dynamic random access memory array, said data bus, said page mode write control means and said same page detection logic means for latching data from said data bus which is to be written to said dynamic random access memory array using said latch control signal; said page mode write control means, said latch control signal and said latch means cooperatively operating to provide a single level of write buffering.
Claim 2
Dependent Claim
216 words
A memory system having an address bus and a data bus coupled to a dynamic random access memory array, a memory cache coupled to said address bus and said data bus, a tag array coupled to said address bus and a memory controller coupled to a central processing unit and said dynamic random access memory array, said memory system comprising: a) page mode write control means coupled to said address bus and said memory controller for controlling writes of data on said data bus to said dynamic random access memory array which are within a predetermined memory page; b) same page detection logic means for determining whether consecutive writes of data on said data bus to said dynamic random access memory array are within said predetermined memory page and generating a latch control signal for latching data on said data bus; c) latch means coupled to said dynamic random access memory array, said data bus, said page mode write control means and said same page detection logic means for latching data from said data bus which is to be written to said dynamic random access memory array using said latch control signal; said page mode write control means, said latch control signal and said latch means cooperatively operating to provide a single level of write buffering.
Claim 3
Dependent Claim
45 words
The memory system defined by claim 1 wherein said same page detection logic means latches predetermined high order bits on said address bus for write operations and compares the latched high order bits with predetermined high order bits latched from an immediately prior write operation.
Claim 4
Dependent Claim
71 words
The memory system defined by claim 2 wherein said same page detection logic means generates control signals causing data on the data bus to be written to said memory cache when said compared bits do not match, said control signals causing data on the data bus to be written to said dynamic random access memory array as a page mode write when said two latched predetermined high order bits do match.
Claim 5
Dependent Claim
18 words
The system defined by claim 1 wherein said same page detection logic means comprises a finite state machine.
Claim 6
Dependent Claim
18 words
The system defined by claim 1 wherein said page mode write control means comprises a finite state machine.
Claim 7
Independent Claim
161 words
A method for controlling the operation of a memory system having an address bus and a data bus coupled to a dynamic random access memory array, a memory cache coupled to said address bus and said data bus, a tag array coupled to said address bus and a memory controller coupled to a central processing unit and said dynamic random access memory array, said method comprising the steps of: a) controlling writes of data on said data bus to said dynamic random access memory array which are within a predetermined memory page; b) determining whether consecutive writes of data on said data bus to said dynamic random access memory array are within said predetermined memory page and generating a latch control signal for latching data on said data bus; c) latching data from said data bus which is to be written to said dynamic random access memory array using said latch control signal to provide a single level of write buffering.
Claim 8
Independent Claim
161 words
A method for controlling the operation of a memory system having an address bus and a data bus coupled to a dynamic random access memory array, a memory cache coupled to said address bus and said data bus, a tag array coupled to said address bus and a memory controller coupled to a central processing unit and said dynamic random access memory array, said method comprising the steps of: a) controlling writes of data on said data bus to said dynamic random access memory array which are within a predetermined memory page; b) determining whether consecutive writes of data on said data bus to said dynamic random access memory array are within said predetermined memory page and generating a latch control signal for latching data on said data bus; c) latching data from said data bus which is to be written to said dynamic random access memory array using said latch control signal to provide a single level of write buffering.
Claim 9
Dependent Claim
47 words
The method defined by claim 6 wherein said determining step comprises the steps of: a) latching predetermined high order bits on said address bus for write operations; and b) comparing the latched high order bits with predetermined high order bits latched from an immediately prior write operation.
Claim 10
Dependent Claim
67 words
The method defined by claim 7 wherein said determining step comprises the step of: generating control signals which cause data on the data bus to be written to said memory cache when said compared bits do not match, and which cause data on the data bus to be written to said dynamic random access memory array as a page mode write when said compared bits do match.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-19 | 1999-08-21 | 2000-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-19 | 2003-08-21 | 2004-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-19 | 2007-08-21 | 2008-02-20 | $7700.00 | Window Closed / Lapsed |