US5493570A
Expired / Lapsed
US
⏱️ 0.0 years remaining
End of packet detector and resynchronizer for serial data buses
Assignee: Apple Inc
•
Filing: 1995-03-15
•
Granted: 1996-02-20
•
Expires: 2015-03-15
Abstract
Abstract An interface device for a point-to-point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmissions of packets of data, includes a low latency resynchronizing circuit and an end of packet detector which is independent of control data within the packet. The resynchronizer is based on an interface which receives bus data and bus clock from a transmission of a packet on the bus. A circular input buffer stores bus data received from the bus in data locations indicated by an input pointer in response to the bus clock. An input pointer generator supplies the input pointers to the input buffer in a circular sequence, beginning in a particular location during a first bus clock in a packet. An output selector supplies bus data from one of the N data locations in the input buffer to the selector output in response to an output pointer and in response to the local clock. An output pointer generator supplies the output pointer in a circular sequence beginning in the particular location in a local clock cycle after the first bus clock in the packet. The end of packet is detected using a comparator coupled to the input pointer generator and the output pointer generator. When the input pointer and the output pointer match, the end of the data packet is indicated. The overrun only occurs after the bus clock has stopped at the end of the packet which stops the output pointer generator.
Inventors
- 👤 Daniel L. Hillman
- 👤 Michael Teener
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:29
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/403; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0632; H04L7/00; H04L7/0008; H04L7/0012; H04L7/02; H04L7/033; H04L7/0337; H04L7/0338
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
100 words
An interface device for a point to point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmission of packets of data, comprising: a local clock source to supply a local clock; means, coupled to the bus and receiving the local clock, for resynchronizing data on the bus with the local clock; and means, coupled to the bus, for detecting an end of a packet of data independent of control data for the packet which provides a low latency indication that the interface device is available to receive a next packet of data.
Claim 2
Dependent Claim
100 words
An interface device for a point to point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmission of packets of data, comprising: a local clock source to supply a local clock; means, coupled to the bus and receiving the local clock, for resynchronizing data on the bus with the local clock; and means, coupled to the bus, for detecting an end of a packet of data independent of control data for the packet which provides a low latency indication that the interface device is available to receive a next packet of data.
Claim 3
Dependent Claim
37 words
The interface device of claim 1, further including: means, coupled to the means for resynchronizing, for transmitting resynchronized data on the bus or accepting resynchronized data for local processing in response to control data in the packet.
Claim 4
Dependent Claim
36 words
The interface device of claim 2, further including: means, coupled to the means for resynchronizing, for detecting errors in a packet of resynchronized data accepted for local processing in response to control data in the packet.
Claim 5
Dependent Claim
169 words
An interface device for a point to point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmission of packets of data, comprising: a local clock source to supply a local clock; means, coupled to the bus and receiving the local clock, for resynchronizing data on the bus with the local clock; means, coupled to the means for resynchronizing, for transmitting resynchronized data on the bus or accepting resynchronized data for local processing in response to control data in the packet; means, coupled to the means for resynchronizing, for detecting an end of a packet of data independent of control data in the packet which provides a low latency indication that the interface device is available for receiving a next packet of data; and means, coupled to the means for resynchronizing and the means for detecting an end of a packet, for detecting errors in a packet of resynchronized data accepted for local processing in response to control data in the packet.
Claim 6
Dependent Claim
169 words
An interface device for a point to point connected serial bus in which bus clock and bus data transmissions on the bus cease between transmission of packets of data, comprising: a local clock source to supply a local clock; means, coupled to the bus and receiving the local clock, for resynchronizing data on the bus with the local clock; means, coupled to the means for resynchronizing, for transmitting resynchronized data on the bus or accepting resynchronized data for local processing in response to control data in the packet; means, coupled to the means for resynchronizing, for detecting an end of a packet of data independent of control data in the packet which provides a low latency indication that the interface device is available for receiving a next packet of data; and means, coupled to the means for resynchronizing and the means for detecting an end of a packet, for detecting errors in a packet of resynchronized data accepted for local processing in response to control data in the packet.
Claim 7
Dependent Claim
109 words
An interface circuit for a local device coupled to a serial bus that carries a packet transmission including a sequence of data values and an input clock, the interface circuit comprising: input buffer that buffers the sequence of data values in response to the input clock; output circuit that transfers the sequence of data values from the input buffer to the local device in response to a local clock; resynchronizer circuit that provides a low latency indication of when the input buffer is available for a next packet transmission on the serial bus by detecting an end of the packet transmission independent of control information in the packet transmission.
Claim 8
Dependent Claim
109 words
An interface circuit for a local device coupled to a serial bus that carries a packet transmission including a sequence of data values and an input clock, the interface circuit comprising: input buffer that buffers the sequence of data values in response to the input clock; output circuit that transfers the sequence of data values from the input buffer to the local device in response to a local clock; resynchronizer circuit that provides a low latency indication of when the input buffer is available for a next packet transmission on the serial bus by detecting an end of the packet transmission independent of control information in the packet transmission.
Claim 9
Dependent Claim
24 words
The interface circuit of claim 5, wherein the resynchronizer circuit generates an end of packet signal after detecting the end of the packet transmission.
Claim 10
Dependent Claim
24 words
The interface circuit of claim 6, further comprising a state machine that resets the input buffer in response to the end of packet signal.
Claim 11
Dependent Claim
32 words
The interface circuit of claim 7, wherein the resynchronizer circuit includes a delay circuit that prevents an erroneous overrun condition if the input clock and the local clock drift toward one another.
Claim 12
Dependent Claim
46 words
The interface circuit of claim 8, wherein the resynchronizer circuit includes an input pointer generator that generates in input pointer in response to the input clock, the input pointer for specifying a sequence of entries in the input buffer for buffering the sequence of data values.
Claim 13
Dependent Claim
50 words
The interface circuit of claim 9, wherein the output circuit includes an output pointer generator that generates in output pointer in response to the local clock, the output pointer for specifying a sequence of entries in the input buffer for transferring the sequence of data values to the local device.
Claim 14
Dependent Claim
28 words
The interface circuit of claim 10, wherein the resynchronizer circuit includes a comparator that generates the end of packet signal if the input pointer equals the output pointer.
Claim 15
Dependent Claim
35 words
The interface circuit of claim 11, wherein the delay circuit ensures that the output pointer lags the input pointer by at least one cycle of the local clock at a start of the packet transmission.
References Cited (Backward Citations)
US4429386A
Cited
FR2579047A1
Cited
JPS61243527A
Cited
US4873703A
Cited
US4884286A
Cited
US4748588A
Cited
EP0270978A2
Cited
US4964142A
Cited
US4933932A
Cited
US4891788A
Cited
WO1990004294A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-19 | 1999-08-21 | 2000-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-19 | 2003-08-21 | 2004-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-19 | 2007-08-21 | 2008-02-20 | $7700.00 | Window Closed / Lapsed |