Method for fabricating a stacked capacitor cell in semiconductor memory device

Claim 1

A method for the fabrication of a semiconductor memory device, comprising the steps of: (A) growing a field oxide layer in a LOCOS step on a semiconductor wafer provided with a P-well and forming a MOSFET having an active region of LDD structure; (B) depositing a blanket insulating oxide film over the resulting structure after step (A), planarizing the blanket insulating oxide film by etching, depositing a barrier silicon nitride and a first storage electrode polysilicon in sequence, and selectively etching the first storage electrode polysilicon, the barrier silicon nitride and the insulating oxide film with a mask for contact hole, to form a groove; (C) depositing a polysilicon layer over the resulting structure after step (B), subjecting the polysilicon layer to anisotropic etching, to form a polysilicon spacer at a side wall of the groove, etching the insulating oxide film, to form a contact hole with both the first storage electrode polysilicon and the polysilicon spacer serving as a mask, then forming an impurity-doped, second storage electrode polysilicon such that it is connected with a source region of the MOSFET, coating a photosensitive film on the second storage electrode polysilicon, and exposing the photosensitive film to light twice with a mask for contact hole and a mask for storage electrode, to form a photosensitive film pattern; (D) selectively etching the second storage polysilicon by use of the photosensitive film pattern as a mask, to form a pattern of second storage polysilicon, removing the photosensitive film pattern, depositing a blanket oxide film over the pattern of second storage polysilicon and subjecting the blanket oxide film to anisotropic etching, to form a sacrificial oxide spacer at a side wall of the pattern of second storage electrode polysilicon; (E) selectively etching the first storage electrode polysilicon and the pattern of second storage electrode polysilicon until the barrier silicon nitride is exposed with the sacrificial oxide spacer serving as a mask; (F) depositing a third storage electrode polysilicon, to cover the sacrificial oxide spacer completely, subjecting the third storage electrode polysilicon to anisotropic etching to such an extent that an upper portion of the sacrificial oxide spacer is exposed, so as to form a pattern of third storage electrode polysilicon at a flank of the sacrificial oxide spacer, said pattern of third storage electrode polysilicon having a structure comprised of a spacer-shaped hollow cylinder and a spacer-shaped solid cylinder present in the central area of the spacer-shaped hollow cylinder and over the contact hole, and removing the sacrificial oxide spacer by wet etching with the barrier silicon nitride serving as an etch stopper; and (G) growing a dielectric layer on the first, second and third storage electrode polysilicons, depositing an impurity-doped polysilicon, and patterning the impurity-doped polysilicon, to form a plate electrode.

Claim 2

A method for the fabrication of a semiconductor memory device, comprising the steps of: (A) growing a field oxide layer in a LOCOS step on a semiconductor wafer provided with a P-well and forming a MOSFET having an active region of LDD structure; (B) depositing a blanket insulating oxide film over the resulting structure after step (A), planarizing the blanket insulating oxide film by etching, depositing a barrier silicon nitride and a first storage electrode polysilicon in sequence, and selectively etching the first storage electrode polysilicon, the barrier silicon nitride and the insulating oxide film with a mask for contact hole, to form a groove; (C) depositing a polysilicon layer over the resulting structure after step (B), subjecting the polysilicon layer to anisotropic etching, to form a polysilicon spacer at a side wall of the groove, etching the insulating oxide film, to form a contact hole with both the first storage electrode polysilicon and the polysilicon spacer serving as a mask, then forming an impurity-doped, second storage electrode polysilicon such that it is connected with a source region of the MOSFET, coating a photosensitive film on the second storage electrode polysilicon, and exposing the photosensitive film to light twice with a mask for contact hole and a mask for storage electrode, to form a photosensitive film pattern; (D) selectively etching the second storage polysilicon by use of the photosensitive film pattern as a mask, to form a pattern of second storage polysilicon, removing the photosensitive film pattern, depositing a blanket oxide film over the pattern of second storage polysilicon and subjecting the blanket oxide film to anisotropic etching, to form a sacrificial oxide spacer at a side wall of the pattern of second storage electrode polysilicon; (E) selectively etching the first storage electrode polysilicon and the pattern of second storage electrode polysilicon until the barrier silicon nitride is exposed with the sacrificial oxide spacer serving as a mask; (F) depositing a third storage electrode polysilicon, to cover the sacrificial oxide spacer completely, subjecting the third storage electrode polysilicon to anisotropic etching to such an extent that an upper portion of the sacrificial oxide spacer is exposed, so as to form a pattern of third storage electrode polysilicon at a flank of the sacrificial oxide spacer, said pattern of third storage electrode polysilicon having a structure comprised of a spacer-shaped hollow cylinder and a spacer-shaped solid cylinder present in the central area of the spacer-shaped hollow cylinder and over the contact hole, and removing the sacrificial oxide spacer by wet etching with the barrier silicon nitride serving as an etch stopper; and (G) growing a dielectric layer on the first, second and third storage electrode polysilicons, depositing an impurity-doped polysilicon, and patterning the impurity-doped polysilicon, to form a plate electrode.