Connector for integrated circuit chips

Claim 2

A connector for electrically coupling first and second groups of circuit contact points formed on first and second integrated electronic circuit chips respectively, comprising: a connector board having a first and second side and being formed of a dielectric material, said connector board having a plurality of openings formed therethrough; and a matching plurality of electroplated conductive members each extending through one of said openings and having an anchor portion on said second side of said connector board, said anchor having a larger lateral dimension than the opening, each of said conductive members further having a via portion extending from the anchor through said opening and expanding laterally onto said first side of said connector board to form a head portion having a lateral dimension larger than said opening, said anchors and head portions being arranged to align with and contact said first and second group of circuit contact points formed on said first and second integrated electronic circuit chips, respectively, and to position said first and second integrated electronic circuit chips in a spaced relationship from said connector board to allow heat dissipation.

Claim 3

The connector as set fourth in claim 1, wherein said dielectric material has a thickness substantially within the range of 0.0005 to 0.005 inches and wherein each of said electroplated conductive members is separated from an adjacent electroplated conductive member by a distance substantially within the range of 0.001 to 0.005 inches.

Claim 4

A connector for electrically coupling first and second groups of circuit contact points formed on first and second integrated electronic circuit chips respectively, comprising: a connector board having a first and second side and being formed of a dielectric material, said connector board having a first and second group of openings formed therethrough, said first group of openings being laterally spaced from said second group of openings; a first and second group of electroplated conductive members each extending through one of said openings and each having an anchor portion on said second side of said connector board, each of said anchors having a larger lateral dimension than said one of said openings, each of said conductive members further having a via portion extending from the anchor through the opening and a head portion, connected to said via, which extends laterally onto said first side of said connector board, each head portion having a lateral dimension larger than said opening; and a third group of conducting members located on said second side of said connector board each extending laterally from one of said first group of anchors to one of said second group of anchors, said head portions being arranged to align with and contact said first and second group of circuit contact points formed on said first and second integrated electronic circuit chips, respectively, said head portions and said anchor portions positioning said first and second integrated electronic circuits chips in a spaced relationship from said connector board to allow heat dissipation.

Claim 5

A connector for electrically coupling first and second groups of circuit contact points formed on first and second integrated electronic circuit chips respectively, comprising: a connector board having a first and second side and being formed of a dielectric material, said connector board having a first and second group of openings formed therethrough, said first group of openings being laterally spaced from said second group of openings; a first and second group of electroplated conductive members each extending through one of said openings and each having an anchor portion on said second side of said connector board, each of said anchors having a larger lateral dimension than said one of said openings, each of said conductive members further having a via portion extending from the anchor through the opening and a head portion, connected to said via, which extends laterally onto said first side of said connector board, each head portion having a lateral dimension larger than said opening; and a third group of conducting members located on said second side of said connector board each extending laterally from one of said first group of anchors to one of said second group of anchors, said head portions being arranged to align with and contact said first and second group of circuit contact points formed on said first and second integrated electronic circuit chips, respectively, said head portions and said anchor portions positioning said first and second integrated electronic circuits chips in a spaced relationship from said connector board to allow heat dissipation.

Claim 6

The connector as set forth in claim 3, wherein said dielectric material has a thickness substantially within the range of 0.0005 to 0.005 inches.

Claim 7

The connector as set forth in claim 3, wherein each of said electroplated conductive members is separated from an adjacent electroplated conductive member by a distance substantially within the range of 0.001 to 0.005 inches.

Claim 8

The connector as set forth in claim 3, wherein said first and second circuit chips have a plurality of edges, said groups of contact points being arranged along more than one said edges, said connector serving to electrically couple contact points formed along more than one of said edges.

Claim 9

An electronic circuit for maximizing use of circuit board surface area comprising: a first integrated circuit chip including a first group of contact points on a lower surface thereof for connecting said first chip to said circuit board and a second and third group of contacts on an upper surface thereof; a second integrated circuit chip including fourth and fifth groups of contact points on a lower surface thereof; and connecting means located between said first and second chips for spacing said first and second chips to allow heat dissipation and for connecting said second group of contact points with said fourth group of contact points and said third group of contact points with said fifth group of contact points, wherein said connecting means includes a connector board formed of a dielectric and having first and second openings extending from an upper surface to a lower surface thereof, first and second conductive members each including an anchor portion adjacent said lower surface, a head portion adjacent said upper surface, and a via portion, located in one of said first and second openings, connecting said anchor portion with said head portion, wherein said anchor portion and said head portion have a lateral dimension larger said first and second openings, and wherein said first and second anchor portions are aligned and in contact with said second and third group of contact points, and said first and second head portions are aligned and in contact with said fourth and fifth group of contact points.

Claim 10

An electronic circuit for maximizing use of circuit board surface area comprising: a first integrated circuit chip including a first group of contact points on a lower surface thereof for connecting said first chip to said circuit board and a second and third group of contacts on an upper surface thereof; a second integrated circuit chip including fourth and fifth groups of contact points on a lower surface thereof; and connecting means located between said first and second chips for spacing said first and second chips to allow heat dissipation and for connecting said second group of contact points with said fourth group of contact points and said third group of contact points with said fifth group of contact points, wherein said connecting means includes a connector board formed of a dielectric and having first and second openings extending from an upper surface to a lower surface thereof, first and second conductive members each including an anchor portion adjacent said lower surface, a head portion adjacent said upper surface, and a via portion, located in one of said first and second openings, connecting said anchor portion with said head portion, wherein said anchor portion and said head portion have a lateral dimension larger said first and second openings, and wherein said first and second anchor portions are aligned and in contact with said second and third group of contact points, and said first and second head portions are aligned and in contact with said fourth and fifth group of contact points.

Claim 11

The electronic circuit of claim 7 wherein said first integrated circuit chip includes a via connecting said first group of contact points with at least one of said second and third group of contact points.

Claim 12

A connector for maximizing use of circuit board surface area by connecting a first group of contact points of a first integrated circuit chip to a second group of contact points of a circuit board comprising: a first connector board formed of a dielectric and having a first and second group of openings extending from an upper surface to a lower surface thereof, wherein said first group of openings is laterally spaced from said second group of openings; a first and second group of conductive members each including an anchor portion adjacent said upper surface, a head portion adjacent said lower surface, and a via portion connecting said anchor portion with said head portion, said first and second groups of conductive members being located in said first and second groups of openings, said anchor portion and said head portion having a lateral dimension larger said first and second openings; and a third group of conducting members connecting said first group of anchors to said second group of anchors.

Claim 13

A connector for maximizing use of circuit board surface area by connecting a first group of contact points of a first integrated circuit chip to a second group of contact points of a circuit board comprising: a first connector board formed of a dielectric and having a first and second group of openings extending from an upper surface to a lower surface thereof, wherein said first group of openings is laterally spaced from said second group of openings; a first and second group of conductive members each including an anchor portion adjacent said upper surface, a head portion adjacent said lower surface, and a via portion connecting said anchor portion with said head portion, said first and second groups of conductive members being located in said first and second groups of openings, said anchor portion and said head portion having a lateral dimension larger said first and second openings; and a third group of conducting members connecting said first group of anchors to said second group of anchors.

Claim 14

The connector of claim 9 further comprising: a third and fourth group of openings in said connector board extending from an upper surface to a lower surface thereof, wherein said third group of openings is laterally spaced from said fourth group of openings, said third and fourth group of openings being spaced from said first and second group of openings; a fourth and fifth group of conductive members each including an anchor portion adjacent said upper surface, a head portion adjacent said lower surface, and a via portion connecting said anchor portion with said head portion, said fourth and fifth groups of conductive members being located in said fourth and fifth groups of openings, said anchor portion and said head portion having a lateral dimension larger than said fourth and fifth openings; and a sixth group of conductive members connecting said fourth group of anchors to said fifth group of anchors.

Claim 15

The connector of claim 9 further comprising: a first spacer located adjacent said first chip and between said circuit board and said first connector board, said first spacer being formed of a dielectric and including a fifth group of openings and a seventh group of conducting members, located in said fifth group of openings, each with an anchor portion, a head portion, and a via connecting said anchor portion with said head portion, wherein said head portion and said anchor portion have a larger lateral dimension than said fifth group of openings and wherein said first, second, third and seventh group of conductive members connect said first group of contact points of said circuit board with said second group of contact points of said first chip.

Claim 16

A modular electronic circuit for maximizing use of circuit board surface area by connecting multiple chips to first and second groups of contact points of a circuit board, comprising: first and second spacers, located adjacent one surface of said circuit board, including a first and second group of conductive members, respectively, said first and second groups of conductive members of said first and second spacers being connected to said first and second groups of contact points, respectively; a first connector board, located adjacent said first and second spacers, including a first and second group of U-shaped conducting members, wherein a first end of said first group of U-shaped conducting members projects from one side of said first connector board and is connected to said first group of conductive members of said first spacer, and a first end of said second group of U-shaped conducting members projects from said one side of said first connector board and is connected to said second group of conductive members of said second spacer; and a first chip, located between said one side of said first connector board and said circuit board and between said first and second spacers, including a third and fourth group of contact points, said third group of contact points being laterally spaced from said fourth group of contact points, wherein a second end of said first and second U-shaped conducting members projects from said one side of said first connector board, is laterally spaced from said first ends and is connected to said third and fourth group of contact points of said first chip, respectively.

Claim 17

A modular electronic circuit for maximizing use of circuit board surface area by connecting multiple chips to first and second groups of contact points of a circuit board, comprising: first and second spacers, located adjacent one surface of said circuit board, including a first and second group of conductive members, respectively, said first and second groups of conductive members of said first and second spacers being connected to said first and second groups of contact points, respectively; a first connector board, located adjacent said first and second spacers, including a first and second group of U-shaped conducting members, wherein a first end of said first group of U-shaped conducting members projects from one side of said first connector board and is connected to said first group of conductive members of said first spacer, and a first end of said second group of U-shaped conducting members projects from said one side of said first connector board and is connected to said second group of conductive members of said second spacer; and a first chip, located between said one side of said first connector board and said circuit board and between said first and second spacers, including a third and fourth group of contact points, said third group of contact points being laterally spaced from said fourth group of contact points, wherein a second end of said first and second U-shaped conducting members projects from said one side of said first connector board, is laterally spaced from said first ends and is connected to said third and fourth group of contact points of said first chip, respectively.

Claim 18

The modular electronic circuit of claim 12 further comprising: third and fourth spacers, located adjacent an opposite side of said first connector, including a third and fourth group of conductive members, respectively, which are connected to middle portions of said first and second U-shaped conductive members, respectively, which are located on said opposite side of said first connector board; a second connector board, located adjacent said third and fourth spacers, including a third and fourth group of U-shaped conducting members, wherein a first end of said third group of U-shaped conducting members projects from one side of said second connector board and is connected to said third group of conductive members of said third spacer; and a second chip, located between said one side of said second connector board and said opposite side of said first connector board, including a fifth and sixth group of contact points, said fifth group of contact points being laterally spaced from said sixth group of contact points, wherein a second end of said third and fourth U-shaped conducting members projects from said one side of said second connector board and is connected to said fifth and sixth group of contact points of said second chip.

Claim 19

A modular electronic circuit for maximizing use of circuit board surface area by connecting multiple chips to a first group of contact points on one side of a circuit board, comprising: a first spacer, located adjacent said one side of said circuit board, including a first group of conductive members connected to said first group of contact points of said circuit board; a first connector, located adjacent said first spacer, including a first group of U-shaped conducting members, wherein a first end of said first group of U-shaped conducting members projects from one side of said first connector and is connected to said first group of conductive members of said first spacer; and a first integrated circuit chip, located between said first connector and said circuit board and adjacent said first spacer, including a second group of contact points, wherein a second end of said first U-shaped conducting members projects from said one side of said first connector and is connected to said second group of contact points of said first chip, whereby said first spacer and said first connector electrically connect said first group of contact points of said circuit board to said second group of contact points of said first integrated circuit chip and support said first chip in a spaced relationship relative to said circuit board to allow heat dissipation.

Claim 20

A modular electronic circuit for maximizing use of circuit board surface area by connecting multiple chips to a first group of contact points on one side of a circuit board, comprising: a first spacer, located adjacent said one side of said circuit board, including a first group of conductive members connected to said first group of contact points of said circuit board; a first connector, located adjacent said first spacer, including a first group of U-shaped conducting members, wherein a first end of said first group of U-shaped conducting members projects from one side of said first connector and is connected to said first group of conductive members of said first spacer; and a first integrated circuit chip, located between said first connector and said circuit board and adjacent said first spacer, including a second group of contact points, wherein a second end of said first U-shaped conducting members projects from said one side of said first connector and is connected to said second group of contact points of said first chip, whereby said first spacer and said first connector electrically connect said first group of contact points of said circuit board to said second group of contact points of said first integrated circuit chip and support said first chip in a spaced relationship relative to said circuit board to allow heat dissipation.

Claim 21

The modular electronic circuit of claim 14 further comprising: a second spacer, located adjacent said circuit board, including a second group of conductive members connected to a middle portion of said first U-shaped conductive member lying along an opposite surface of said first connector; a second connector, located adjacent said second spacer, including a second group of U-shaped conducting members, wherein a first end of said second group of U-shaped conducting members projects from one side of said second connector and is connected to said second group of conductive members of said second spacer; and a second chip, located between said second connector and said first connector and adjacent said second spacer, including a third group of contact points wherein a second end of said second U-shaped conducting members projects from said one side of said second connector and is connected to said third group of contact points of said second chip.