Current-controlled quadrature oscillator based on differential gm /C cells

Claim 2

An oscillator comprising: a first gm/C integrator stage having a first pair of input terminals, a first pair of output terminals, and a first pair of common-mode terminals; a first common-mode biasing means coupled between a supply voltage and the first pair of common-mode terminals; a second gm/C integrator stage having a second pair of input terminals, a second pair of output terminals, and a second pair of common-mode terminals; a second common-mode biasing means coupled between a supply voltage and the second pair of common-mode terminals; and wherein the first pair of output terminals is coupled to the second pair of input terminals and the second pair of output terminals is cross-coupled to the first pair of input terminals such that a signal appearing on the first pair of input terminals is 180 degrees out of phase with a concomitant signal appearing on the second pair of input terminals whereby the oscillator oscillates.

Claim 3

An oscillator according to claim 1 further including: a first start-up means coupled to the first pair of output terminals; and a second start-up means coupled to the second pair of output terminals.

Claim 4

An oscillator according to claim 2 wherein the first start-up means includes means for producing a negative resistance, wherein the absolute value of the negative resistance is equal to or greater than the absolute value of an input resistance of the second gm/C integrator stage.

Claim 5

An oscillator according to claim 2 wherein the first start-up means includes: a pair of cross-coupled transistors; and a current source coupled to the pair of cross-coupled transistors for providing a bias current thereto.

Claim 6

An oscillator according to claim 2 further including means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals.

Claim 7

An oscillator according to claim 5 wherein the means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals includes a first pair of amplitude limiting diodes, wherein each one of the first pair of amplitude limiting diodes is coupled between the supply voltage and a respective one of the first pair of output terminals.

Claim 8

An oscillator according to claim 2 wherein the first common-mode biasing means includes a first pair of biasing resistors, each one of the first pair of biasing resistors coupled between the supply voltage and a respective one of the first pair of output terminals.

Claim 9

An oscillator according to claim 2 wherein the first common-mode biasing means includes a first pair of biasing diodes connected in series and a second pair of biasing diodes connected in series, each pair of biasing diodes coupled between the supply voltage and a respective one of the first pair of output terminals.

Claim 10

An oscillator according to claim 1 wherein the first common-mode biasing means includes: a first current mirror including a first diode-connected transistor having a base and being coupled between the supply voltage and a first one of the first pair of output terminals and including a first mirror transistor having a base and being coupled between the supply voltage and a second one of the first pair of output terminals, the base of the first diode-connected transistor being coupled to the base of the first mirror transistor; and a second current mirror including a second diode-connected transistor having a base and being coupled between the supply voltage and the second one of the first pair of output terminals and including a second mirror transistor having a base and being coupled between the supply voltage and the first one of the first pair of output terminals, the base of the second diode-connected transistor being coupled to the base of the second mirror transistor.

Claim 11

An oscillator according to claim I wherein the first gm/C integrator stage includes a first multi-tanh n-tuplet.

Claim 12

An oscillator comprising: a first gm/C integrator stage having a first pair of input terminals, a first pair of output terminals, and a first pair of common-mode terminals; a first pair of common-mode transistors coupled between a supply voltage and the first pair of common-mode terminals, each one of the first pair of common mode transistors being coupled between the supply voltage and a respective one of the first pair of common-mode terminals, each one of the first pair of common mode transistors having a control terminal; a first common-mode biasing transistor having a control terminal coupled to a second gm/C integrator stage and a load terminal coupled to the control terminals of the first pair of common-mode transistors; a first start-up means coupled to the first pair of output terminals; the second gm/C integrator stage having a second pair of input terminals, a second pair of output terminals, and a second pair of common-mode terminals; a second pair of common-mode transistors coupled between the supply voltage and the second pair of common-mode terminals, each one of the second pair of common mode transistors being coupled between the supply voltage and a respective one of the second pair of common-mode terminals, each one of the second pair of common mode transistors having a control terminal; a second common-mode biasing transistor having a control terminal coupled to the first gm/C integrator stage and a load terminal coupled to the control terminals of the second pair of common-mode transistors; and a second start-up means coupled to the second pair of output terminals; wherein the first pair of output terminals is coupled to the second pair of input terminals and the second pair of output terminals is cross-coupled to the first pair of input terminals such that a signal appearing on the first pair of input terminals is 180 degrees out of phase with a concomitant signal appearing on the second pair of input terminals whereby the oscillator oscillates.

Claim 13

An oscillator comprising: a first gm/C integrator stage having a first pair of input terminals, a first pair of output terminals, and a first pair of common-mode terminals; a first pair of common-mode transistors coupled between a supply voltage and the first pair of common-mode terminals, each one of the first pair of common mode transistors being coupled between the supply voltage and a respective one of the first pair of common-mode terminals, each one of the first pair of common mode transistors having a control terminal; a first common-mode biasing transistor having a control terminal coupled to a second gm/C integrator stage and a load terminal coupled to the control terminals of the first pair of common-mode transistors; a first start-up means coupled to the first pair of output terminals; the second gm/C integrator stage having a second pair of input terminals, a second pair of output terminals, and a second pair of common-mode terminals; a second pair of common-mode transistors coupled between the supply voltage and the second pair of common-mode terminals, each one of the second pair of common mode transistors being coupled between the supply voltage and a respective one of the second pair of common-mode terminals, each one of the second pair of common mode transistors having a control terminal; a second common-mode biasing transistor having a control terminal coupled to the first gm/C integrator stage and a load terminal coupled to the control terminals of the second pair of common-mode transistors; and a second start-up means coupled to the second pair of output terminals; wherein the first pair of output terminals is coupled to the second pair of input terminals and the second pair of output terminals is cross-coupled to the first pair of input terminals such that a signal appearing on the first pair of input terminals is 180 degrees out of phase with a concomitant signal appearing on the second pair of input terminals whereby the oscillator oscillates.

Claim 14

An oscillator according to claim 11 wherein the first pair of common-mode transistors include a first pair of lateral PNP transistors.

Claim 15

An oscillator according to claim 11 wherein the first pair of common-mode transistors include a first pair of complementary bipolar PNP transistors.

Claim 16

An oscillator according to claim 11 wherein the first common-mode biasing transistor includes a vertical PNP transistor.

Claim 17

An oscillator according to claim 11 wherein the first start-up means includes: a first pair of cross-coupled transistors coupled to the first pair of output terminals; and a first biasing current source coupled to the first pair of cross-coupled transistors.

Claim 18

An oscillator according to claim 15 further including means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals.

Claim 19

An oscillator according to claim 16 wherein the means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals includes a first pair of amplitude limiting diodes, wherein each one of the first pair of amplitude limiting diodes is coupled between the supply voltage and a respective one of the first pair of output terminals.

Claim 20

An oscillator comprising: a first gm/C integrator stage having a first pair of input terminals, a first pair of output terminals, and a first pair of common-mode terminals; a first common-mode biasing means coupled between a supply voltage and the first pair of common-mode terminals; a first pair of cross-coupled transistors coupled to the first pair of output terminals; a first biasing current source coupled to the first pair of cross-coupled transistors; a second gm/C integrator stage having a second pair of input terminals, a second pair of output terminals, and a second pair of common-mode terminals; a second common-mode biasing means coupled between a supply voltage and the second pair of common-mode terminals; and a second pair of cross-coupled transistors coupled to the second pair of output terminals; and a second biasing current source coupled to the second pair of cross-coupled transistors; wherein the first pair of output terminals is coupled to the second pair of input terminals and the second pair of output terminals is cross-coupled to the first pair of input terminals such that a signal appearing on the first pair of input terminals is 180 degrees out of phase with a concomitant signal appearing on the second pair of input terminals whereby the oscillator oscillates.

Claim 21

An oscillator comprising: a first gm/C integrator stage having a first pair of input terminals, a first pair of output terminals, and a first pair of common-mode terminals; a first common-mode biasing means coupled between a supply voltage and the first pair of common-mode terminals; a first pair of cross-coupled transistors coupled to the first pair of output terminals; a first biasing current source coupled to the first pair of cross-coupled transistors; a second gm/C integrator stage having a second pair of input terminals, a second pair of output terminals, and a second pair of common-mode terminals; a second common-mode biasing means coupled between a supply voltage and the second pair of common-mode terminals; and a second pair of cross-coupled transistors coupled to the second pair of output terminals; and a second biasing current source coupled to the second pair of cross-coupled transistors; wherein the first pair of output terminals is coupled to the second pair of input terminals and the second pair of output terminals is cross-coupled to the first pair of input terminals such that a signal appearing on the first pair of input terminals is 180 degrees out of phase with a concomitant signal appearing on the second pair of input terminals whereby the oscillator oscillates.

Claim 22

An oscillator according to claim 18 further including means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals.

Claim 23

An oscillator according to claim 19 further including means coupled between the supply voltage and the second pair of output terminals for limiting the amplitude of a signal appearing across the second pair of output terminals.

Claim 24

An oscillator according to claim 19 wherein the means coupled between the supply voltage and the first pair of output terminals for limiting the amplitude of a signal appearing across the first pair of output terminals includes a first pair of amplitude limiting diodes, wherein each one of the first pair of amplitude limiting diodes is coupled between the supply voltage and a respective one of the first pair of output terminals.

Claim 25

An oscillator according to claim 18 wherein the first common-mode biasing means coupled between a supply voltage and the first pair of common-mode terminals includes: a first pair of common-mode transistors coupled between a supply voltage and the first pair of common-mode terminals, each one of the first pair of common mode transistors being coupled between the supply voltage and a respective one of the first pair of common-mode terminals, each one of the first pair of common mode transistors having a control terminal; and a first common-mode biasing transistor having a control terminal coupled to the second gm/C integrator stage and a load terminal coupled to the control terminals of the first pair of common-mode transistors.

Claim 26

An oscillator according to claim 18 wherein the first common-mode biasing means coupled between a supply voltage and the first pair of common-mode terminals includes: a first current mirror including a first diode-connected transistor having a base and being coupled between the supply voltage and a first one of the first pair of output terminals and including a first mirror transistor having a base and being coupled between the supply voltage and a second one of the first pair of output terminals, the base of the first diode-connected transistor being coupled to the base of the first mirror transistor; and a second current mirror including a second diode-connected transistor having a base and being coupled between the supply voltage and the second one of the first pair of output terminals and including a second mirror transistor having a base and being coupled between the supply voltage and the first one of the first pair of output terminals, the base of the second diode-connected transistor being coupled to the base of the second mirror transistor.

Claim 27

An oscillator according to claim 23 wherein the first diode-connected transistor is a PNP transistor having a base, an emitter, and a collector, the emitter of the first diode-connected transistor being coupled to the supply voltage and the collector of the first diode-connected transistor being coupled to one of the first pair of output terminals; wherein the first mirror transistor is a PNP transistor having a base, an emitter, and a collector, the emitter of the first mirror transistor being coupled to the supply voltage and the collector of the first mirror transistor being coupled to the other one of the first pair of output terminals; and wherein the base of the first diode-connected transistor is coupled to the base of the first mirror transistor.

Claim 28

An oscillator according to claim 24 wherein the ratio of the first diode-connected transistor emitter area to the first mirror transistor emitter area is equal to 1:1+δ.

Claim 29

An oscillator according to claim 18 wherein the first gm/C integrator stage includes: a first differential pair of transistors, each transistor having a base, a collector, and an emitter, wherein the collectors of the differential pair comprise the first pair of output terminals; a first capacitor coupled across the first pair of output terminals; and a first controllable current source coupled to the emitters of the differential pair of transistors, wherein the frequency of oscillation is responsive to the current in the first controllable current source.

Claim 30

An oscillator according to claim 26 wherein the first capacitor includes a pair of capacitors connected in parallel.

Claim 31

An oscillator comprising: a first gm/C integrator stage having a first pair of input terminals, a first pair of output terminals, and a first pair of common-mode terminals; a first common-mode biasing circuit coupled between a supply voltage and the first pair of common-mode terminals; a second gm/C integrator stage having a second pair of input terminals, a second pair of output terminals, and a second pair of common-mode terminals; a second common-mode biasing circuit coupled between a supply voltage and the second pair of common-mode terminals; and wherein the first pair of output terminals is coupled to the second pair of input terminals and the second pair of output terminals is cross-coupled to the first pair of input terminals such that a signal appearing on the first pair of input terminals is 180 degrees out of phase with a concomitant signal appearing on the second pair of input terminals whereby the oscillator oscillates.

Claim 32

An oscillator comprising: a first gm/C integrator stage having a first pair of input terminals, a first pair of output terminals, and a first pair of common-mode terminals; a first common-mode biasing circuit coupled between a supply voltage and the first pair of common-mode terminals; a second gm/C integrator stage having a second pair of input terminals, a second pair of output terminals, and a second pair of common-mode terminals; a second common-mode biasing circuit coupled between a supply voltage and the second pair of common-mode terminals; and wherein the first pair of output terminals is coupled to the second pair of input terminals and the second pair of output terminals is cross-coupled to the first pair of input terminals such that a signal appearing on the first pair of input terminals is 180 degrees out of phase with a concomitant signal appearing on the second pair of input terminals whereby the oscillator oscillates.

Claim 33

An oscillator according to claim 28 wherein the first common mode biasing circuit comprises: a first biasing transistor being coupled between the supply voltage and a first one of the first pair of common mode terminals, the first biasing transistor having a control terminal coupled to a second one of the first pair of common mode terminals; a first diode coupled between the supply voltage and the control terminal of the first biasing transistor; a second biasing transistor being coupled between the supply voltage and the second one of the first pair of common mode terminals, the second biasing transistor having a control terminal coupled to the first one of the first pair of common mode terminals; and a second diode coupled between the supply voltage and the control terminal of the second biasing transistor.

Claim 34

An oscillator according to claim 28 further comprising means for tuning the oscillator.

Claim 35

An oscillator according to claim 30 wherein the means for tuning the oscillator includes: a tuning transistor having a control terminal, a bias terminal, and a supply terminal, the control terminal for receiving a frequency control signal, the bias terminal being coupled to the first and second gm/C stages for providing a bias current thereto, and the supply terminal being coupled to the supply voltage.

Claim 36

An oscillator according to claim 31 wherein the means for tuning the oscillator further includes: a capacitor coupled between the control terminal and the bias terminal of the tuning transistor; and a biasing transistor coupled to the tuning transistor.

Claim 37

An oscillator according to claim 31 wherein the first and second gm/C stages include first and second tunable current sources, respectively.

Claim 38

An oscillator according to claim 33 wherein the bias terminal of the tuning transistor is coupled to the first and second tunable current sources to modulate the current supplied by the tunable current sources, wherein the frequency of oscillation modulates responsive thereto.

Claim 41

A method of tuning an oscillation frequency of an oscillator according to claim 35 including starting up the oscillator.

Claim 42

A method of tuning an oscillation frequency of an oscillator according to claim 36 wherein the step of starting up the oscillator includes locating a pole for each gm/C stage in the right hand plane.

Claim 43

A method of tuning an oscillation frequency of an oscillator according to claim 37 wherein the step of locating a pole for each gm/C stage in the right hand plane includes providing a negative impedance to each gm/C stage.

Claim 44

A method of tuning an oscillation frequency of an oscillator according to claim 35 wherein the step of altering the currents through the gm/C stages responsive to the control signal includes supplying a bias current to the tunable current sources responsive to the control signal.

Claim 45

A method of tuning an oscillation frequency of an oscillator according to claim 35 including providing a common-mode bias current to each of the gm/C stages.

Claim 46

A method of tuning an oscillation frequency of an oscillator according to claim 35 including limiting the amplitude of the oscillation.