Video signal scrambling and descrambling apparatus

Claim 1

An apparatus for scrambling and descrambling a video signal which includes a plurality of horizontal scanning lines, comprising: memory means for storing key data, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said memory means, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, address setting means for scrambling and descrambling, said address setting means set to an initial value corresponding to an output of the PN generator during scrambling, and, set to a further initial value which corresponds to a maximum address value of the plurality of line memories minus a further output of the PN generator during descrambling, and an address counter for generating a plurality of consecutive address values beginning at one of said initial value and said further initial value, and for applying each one of said plurality of consecutive address values respectively to each one of said plurality of line memories for each horizontal scanning line.

Claim 2

An apparatus for scrambling and descrambling a video signal which includes a plurality of horizontal scanning lines, comprising: memory means for storing key data, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said memory means, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, address setting means for scrambling and descrambling, said address setting means set to an initial value corresponding to an output of the PN generator during scrambling, and, set to a further initial value which corresponds to a maximum address value of the plurality of line memories minus a further output of the PN generator during descrambling, and an address counter for generating a plurality of consecutive address values beginning at one of said initial value and said further initial value, and for applying each one of said plurality of consecutive address values respectively to each one of said plurality of line memories for each horizontal scanning line.

Claim 8

An apparatus for scrambling and descrambling a video signal which includes a plurality of horizontal scanning lines, comprising: memory means for storing key data for encrypting, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said memory means, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, address setting means for scrambling and descrambling, said address setting means set to an initial value corresponding to a maximum address value of the plurality of line memories minus an output of the PN generator during scrambling, and set to a further initial value which corresponds to a further output of the PN generator during descrambling, and an address counter for generating a plurality of consecutive address values beginning at one of said initial value and said further initial value, and for applying each one of said plurality of consecutive address values respectively to each one of said plurality of line memories for each horizontal scanning line.

Claim 9

An apparatus for scrambling and descrambling a video signal which includes a plurality of horizontal scanning lines, comprising: memory means for storing key data for encrypting, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said memory means, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, address setting means for scrambling and descrambling, said address setting means set to an initial value corresponding to a maximum address value of the plurality of line memories minus an output of the PN generator during scrambling, and set to a further initial value which corresponds to a further output of the PN generator during descrambling, and an address counter for generating a plurality of consecutive address values beginning at one of said initial value and said further initial value, and for applying each one of said plurality of consecutive address values respectively to each one of said plurality of line memories for each horizontal scanning line.

Claim 16

An apparatus for scrambling and descrambling a video signal including a plurality of horizontal scanning lines, comprising: a first memory for storing key data, a second memory for storing a reloadable code number which includes a plurality of digits, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said first memory and said reloadable code number stored in said second memory, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, an address setting circuit for scrambling and descrambling, said address setting circuit set to an initial value corresponding to an output of the PN generator during scrambling, and set to a further initial value which corresponds to a maximum address value of the plurality of line memories minus a further output of the PN generator during descrambling, and an address counter for generating a plurality of consecutive address values beginning at one of said initial value and said further initial value, and for applying each one of said plurality of consecutive address values respectively to each one of said plurality of line memories for each horizontal scanning line.

Claim 17

An apparatus for scrambling and descrambling a video signal including a plurality of horizontal scanning lines, comprising: a first memory for storing key data, a second memory for storing a reloadable code number which includes a plurality of digits, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said first memory and said reloadable code number stored in said second memory, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, an address setting circuit for scrambling and descrambling, said address setting circuit set to an initial value corresponding to an output of the PN generator during scrambling, and set to a further initial value which corresponds to a maximum address value of the plurality of line memories minus a further output of the PN generator during descrambling, and an address counter for generating a plurality of consecutive address values beginning at one of said initial value and said further initial value, and for applying each one of said plurality of consecutive address values respectively to each one of said plurality of line memories for each horizontal scanning line.

Claim 20

An apparatus for scrambling and descrambling a video signal including a plurality of horizontal scanning lines, comprising: a first memory for storing key data, a second memory for storing a reloadable code number which includes a plurality of digits, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said first memory and said reloadable code number stored in said second memory, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, an address setting circuit for scrambling and descrambling, said address setting circuit set to an initial value corresponding to a maximum address value of the plurality of line memories minus an output of the PN generator during scrambling, and set to a further initial value which corresponds to a further output of the PN generator during descrambling, and an address counter for generating a plurality of consecutive address values beginning at one of said initial value and said further initial value, and for applying each one of said plurality of consecutive address values respectively to each one of said plurality of line memories for each horizontal scanning line.

Claim 21

An apparatus for scrambling and descrambling a video signal including a plurality of horizontal scanning lines, comprising: a first memory for storing key data, a second memory for storing a reloadable code number which includes a plurality of digits, a plurality of line memories, each for storing respective ones of said plurality of horizontal scanning lines, a PN generator, initialized by said key data stored in said first memory and said reloadable code number stored in said second memory, for generating a respective pseudo-random pulse signal for each one of said plurality of horizontal scanning lines, an address setting circuit for scrambling and descrambling, said address setting circuit set to an initial value corresponding to a maximum address value of the plurality of line memories minus an output of the PN generator during scrambling, and set to a further initial value which corresponds to a further output of the PN generator during descrambling, and an address counter for generating a plurality of consecutive address values beginning at one of said initial value and said further initial value, and for applying each one of said plurality of consecutive address values respectively to each one of said plurality of line memories for each horizontal scanning line.

Claim 23

An apparatus according to claims 17, wherein the PN generator includes one of linear feedback shift register and nonlinear feedback shift register.

Claim 25

An apparatus according to claims 1, 7, 14 or 17, wherein the address counter is a read address counter which generates a read address consecutively from the address set by the address setting circuit, and which applies respective read address signals to the plurality of line memories corresponding to said plurality of horizontal scanning lines.

Claim 26

An apparatus according to claims 1, 7, 14 or 17, wherein the address counter is a read address counter which generates a read address consecutively from the address set by the address setting circuit, and which applies respective read address signals to the plurality of line memories corresponding to said plurality of horizontal scanning lines.

Claim 27

An apparatus according to claims 1, 7, 14 or 17, wherein the address counter is a write address counter which generates a write address consecutive from the address set by the address setting circuit, and applies write address signals alternately to the pair of line memories in horizontal scanning line unit.