US5488393A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed video display system
Assignee: Hewlett Packard Development Co LP
•
Filing: 1993-06-23
•
Granted: 1996-01-30
•
Expires: 2013-06-23
Abstract
Abstract A graphics subsystem, including a video digital-to-analog converter, is disclosed. A high speed oscillator generates a pixel clock signal at the frequency at which pixels are to be displayed. Included in the video DAC is a frequency divider which presents an output clock signal having a period which is a multiple of the pixel clock signal, the multiple corresponding to the level of multiplexing of pixel data to be provided by the video DAC; this multiple can equal unity. The video controller in the system receives the output clock signal, and generates clock signals to control the serial port of the frame memory, and also to control the latching of the first stage in the video DAC. The first stage latch in the video DAC latches in the multiple pixel data from the frame memory, and the multiplexer in the video DAC presents the data to the color palette RAM, or around the color palette RAM in true-color non-multiplexed mode, according to the pixel clock signal. As a result, the pixel clock rate is not dependent by the propagation delay of the output clock signal through the video controller, and higher speed system operation is achieved.
Inventors
- 👤 Paul B. Wood
- 👤 Brian F. Bounds
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:09
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/395; G09G5/02; G09G5/06; G09G5/08
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
248 words
A computer system for processing data comprising video data, said computer system comprising: a processor; a video controller; a first bus coupled between said processor and said video controller; a memory for storing video data; a second bus coupled between said video controller and said memory, wherein said video controller is operable to provide said video data to said memory; and a video display driver circuit for driving a display device, comprising: a first clock terminal for receiving a pixel clock signal; a second clock terminal for receiving a latch clock signal; an output clock terminal; a frequency divider circuit, for receiving the pixel clock signal from said first clock terminal, and for presenting, at said output clock terminal, an output clock signal having a period which is a multiple of the period of said pixel clock signal; a plurality of data terminals for receiving said pixel data from said memory; a latch, coupled to said data terminals and to said second clock terminal, for storing pixel data received at said data terminals responsive to said latch clock signal; a multiplexer, having a data input coupled to said latch for receiving said pixel data, having a clock input coupled to receive said pixel clock signal, and having an output, said multiplexer for applying a selected portion of said pixel data to its output responsive to said pixel clock signal; and output circuitry coupled to the output of said multiplexer, for presenting said pixel data to said display device.
Claim 2
Dependent Claim
248 words
A computer system for processing data comprising video data, said computer system comprising: a processor; a video controller; a first bus coupled between said processor and said video controller; a memory for storing video data; a second bus coupled between said video controller and said memory, wherein said video controller is operable to provide said video data to said memory; and a video display driver circuit for driving a display device, comprising: a first clock terminal for receiving a pixel clock signal; a second clock terminal for receiving a latch clock signal; an output clock terminal; a frequency divider circuit, for receiving the pixel clock signal from said first clock terminal, and for presenting, at said output clock terminal, an output clock signal having a period which is a multiple of the period of said pixel clock signal; a plurality of data terminals for receiving said pixel data from said memory; a latch, coupled to said data terminals and to said second clock terminal, for storing pixel data received at said data terminals responsive to said latch clock signal; a multiplexer, having a data input coupled to said latch for receiving said pixel data, having a clock input coupled to receive said pixel clock signal, and having an output, said multiplexer for applying a selected portion of said pixel data to its output responsive to said pixel clock signal; and output circuitry coupled to the output of said multiplexer, for presenting said pixel data to said display device.
Claim 3
Dependent Claim
16 words
The apparatus of claim 1 and further comprising a display device coupled to said output circuitry.
Claim 4
Dependent Claim
28 words
The circuit of claim 1, further comprising: means, coupled to said latch and said multiplexer, for synchronizing the application of said pixel data to said pixel clock signal.
Claim 5
Dependent Claim
72 words
The circuit of claim 1, wherein said output circuitry comprises: a palette memory for storing a plurality of color codes, having an address input coupled to the output of said multiplexer, and having a data output, said palette memory presenting a color code at its data output responsive to receiving pixel data at its address input, said pixel data indicating the address in said palette memory corresponding to the desired color code.
Claim 6
Dependent Claim
51 words
The circuit of claim 1, wherein said output circuitry comprises: a plurality of digital-to-analog converters, each for receiving a portion of said pixel data corresponding to a display component and for converting said received portion of said pixel data to an analog signal corresponding to the intensity of a display component.
Claim 7
Dependent Claim
125 words
The circuit of claim 5, wherein said output circuitry further comprises: a segmented palette memory for storing a plurality of color codes, comprising: a plurality of address inputs, each address input corresponding to a display component and coupled to a portion of the output of said multiplexer; storage locations grouped into a plurality of groups, each group of storage locations corresponding to a display component and addressable according to a value applied to the address input corresponding to its display component; a plurality of data outputs, each corresponding to a display component and coupled to the input of the digital-to-analog converters associated with its display component, for presenting the storage location corresponding to the value applied to the address input corresponding to its display component.
Claim 8
Dependent Claim
27 words
The circuit of claim 1, wherein said frequency divider circuit is controllable to select among a plurality of multiples of said period of said pixel clock signal.
Claim 9
Dependent Claim
31 words
The circuit of claim 1, further comprising: means for selecting the portion of said pixel data to be applied by said multiplexer to its output responsive to said pixel clock signal.
Claim 10
Dependent Claim
21 words
The circuit of claim 8, wherein said selecting means also selects the multiple of said period of said pixel clock signal.
Claim 11
Dependent Claim
219 words
A data processing apparatus, comprising: a video memory, having an output connected to a pixel bus, for presenting pixel data responsive to receiving a memory clock signal; video processing circuitry, coupled to said video memory, for accessing said video memory and for storing data therein corresponding to an image to be displayed; a host processor, coupled to said video processing circuitry by way of a host bus; a clock source for generating a pixel clock signal; a frequency divider circuit, for receiving the pixel clock signal and for generating an output clock signal having a period which is a multiple of the period of said pixel clock signal; a clock controller having an input receiving said output clock signal, for generating said memory clock signal and a latch clock signal based on said output clock signal; a latch, coupled to said pixel bus, for storing pixel data on said pixel bus responsive to said latch clock signal; a multiplexer, having a data input coupled to said latch for receiving said pixel data and having a clock input coupled to receive said pixel clock signal, for selecting a selected portion of said pixel data responsive to said pixel clock signal; and output circuitry coupled to said multiplexer, for presenting said selected portion of said pixel data to said display device.
Claim 12
Dependent Claim
219 words
A data processing apparatus, comprising: a video memory, having an output connected to a pixel bus, for presenting pixel data responsive to receiving a memory clock signal; video processing circuitry, coupled to said video memory, for accessing said video memory and for storing data therein corresponding to an image to be displayed; a host processor, coupled to said video processing circuitry by way of a host bus; a clock source for generating a pixel clock signal; a frequency divider circuit, for receiving the pixel clock signal and for generating an output clock signal having a period which is a multiple of the period of said pixel clock signal; a clock controller having an input receiving said output clock signal, for generating said memory clock signal and a latch clock signal based on said output clock signal; a latch, coupled to said pixel bus, for storing pixel data on said pixel bus responsive to said latch clock signal; a multiplexer, having a data input coupled to said latch for receiving said pixel data and having a clock input coupled to receive said pixel clock signal, for selecting a selected portion of said pixel data responsive to said pixel clock signal; and output circuitry coupled to said multiplexer, for presenting said selected portion of said pixel data to said display device.
Claim 13
Dependent Claim
16 words
The apparatus of claim 10 and further comprising a display device coupled to said output circuitry.
Claim 14
Dependent Claim
28 words
The apparatus of claim 10, further comprising: means, coupled to said latch and said multiplexer, for synchronizing the application of said pixel data to said pixel clock signal.
Claim 15
Dependent Claim
74 words
The apparatus of claim 12, further comprising: a palette memory for storing a plurality of color codes, having an address input coupled to the output of said multiplexer, and having a data output coupled to said output circuitry, said palette memory presenting a color code at its data output responsive to receiving pixel data at its address input, said pixel data indicating the address in said palette memory corresponding to the desired color code.
Claim 16
Dependent Claim
27 words
The apparatus of claim 10, wherein said frequency divider circuit is controllable to select among a plurality of multiples of said period of said pixel clock signal.
Claim 17
Dependent Claim
44 words
The apparatus of claim 14, further comprising: means for selecting the portion of said pixel data to be applied by said multiplexer to its output responsive to said pixel clock signal and for selecting the multiple of said period of said pixel clock signal.
Claim 18
Dependent Claim
120 words
The apparatus of claim 10, wherein said output circuitry comprises: a plurality of digital-to-analog converters, each for receiving a portion of said pixel data corresponding to a display color, each for converting said pixel data to an analog signal corresponding to the intensity of its corresponding display color; and a segmented palette memory for storing a plurality of color codes, comprising: a plurality of address inputs, each coupled to a portion of the output of said multiplexer corresponding to a display color; a plurality of data outputs, each coupled to one of said digital-to-analog converters corresponding to a display color; for presenting a color code responsive to the portion of the output of said multiplexer corresponding to its display color.
References Cited (Backward Citations)
US4364037A
Cited
US4688032A
Cited
US4635048A
Cited
US4660070A
Cited
US4918436A
Cited
US4872002A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-29 | 1999-07-31 | 2000-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-29 | 2003-07-31 | 2004-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-29 | 2007-07-31 | 2008-01-30 | $7700.00 | Window Closed / Lapsed |