US5488246A
Expired / Lapsed
US
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Semiconductor device and method of manufacturing the same
Assignee: Renesas Electronics Corp
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Filing: 1994-04-18
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Granted: 1996-01-30
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Expires: 2014-04-18
Abstract
Abstract A semiconductor device and method of manufacturing the same includes the steps of forming silicon nitride films including much silicon than a stoichiometric silicon nitride (Si 3 N 4 ) and which will be an anti-reflection film, forming a resist film on the plasma silicon nitride films and, and concurrently patterning plasma silicon nitride films and conductive layers and using the resist film as a mask. As a result, high integration of the semiconductor device can be attained.
Inventors
- 👤 Yoshio Hayashide
- 👤 Kouichirou Tsujita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:56
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
167 words
A semiconductor device, comprising: a semiconductor substrate on a main surface of which an element isolating region and an active region are formed; a MOS field effect transistor formed on said active region and having a pair of impurity diffused layers; a conductive layer electrically connected to one of said pair of impurity diffused layers; a first anti-reflection film formed of plasma silicon nitride film including more silicon than a stoichiometrical silicon nitride (Si 3 N 4 ) formed on said conductive layer; an interlayer insulating film having a contact hole reaching the other one of said pair of impurity diffused layers and covering said first anti-reflection film and said MOS field effect transistor; a second anti-reflection film formed of a plasma silicon nitride film including more silicon than the stoichiometrical silicon nitride (Si 3 N 4 ) formed on said interlayer insulating film; and an interconnection layer electrically connected to the other one of said pair of impurity diffused layers formed on said second anti-reflection film.
Claim 2
Dependent Claim
167 words
A semiconductor device, comprising: a semiconductor substrate on a main surface of which an element isolating region and an active region are formed; a MOS field effect transistor formed on said active region and having a pair of impurity diffused layers; a conductive layer electrically connected to one of said pair of impurity diffused layers; a first anti-reflection film formed of plasma silicon nitride film including more silicon than a stoichiometrical silicon nitride (Si 3 N 4 ) formed on said conductive layer; an interlayer insulating film having a contact hole reaching the other one of said pair of impurity diffused layers and covering said first anti-reflection film and said MOS field effect transistor; a second anti-reflection film formed of a plasma silicon nitride film including more silicon than the stoichiometrical silicon nitride (Si 3 N 4 ) formed on said interlayer insulating film; and an interconnection layer electrically connected to the other one of said pair of impurity diffused layers formed on said second anti-reflection film.
Claim 3
Dependent Claim
24 words
The semiconductor device according to claim 1, further comprising a third anti-reflection film formed of Si 3 N 4 under the first anti-reflection film.
Claim 4
Dependent Claim
24 words
The semiconductor device according to claim 2, further comprising a fourth anti-reflection film formed of Si 3 N 4 under the second anti-reflection film.
Claim 5
Dependent Claim
33 words
The semiconductor device according to claim 1, wherein the first and second anti-reflection films are formed of a plasma silicon nitride film Si x N y , wherein 0.75< x / y <1.4.
Claim 6
Dependent Claim
23 words
The semiconductor device according to claim 1, wherein the reflectance of the first and second anti-reflection films is 30% or less upon exposure.
Claim 7
Dependent Claim
70 words
The semiconductor device according to claim 1, wherein the ratio (T 1 /T 2 ) and the ratio (V 1 /V 2 ) is: T.sub.1 /T.sub.2 ≦V.sub.1 /V.sub.2, wherein T 1 is the thickness of the first anti-reflection film, T 2 is the thickness of the conductive layer, V 1 is an etching rate of the first anti-reflection film and V 2 is an etching rate of the conductive layer.
References Cited (Backward Citations)
US5331191A
Cited
US5177581A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-29 | 1999-07-31 | 2000-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-29 | 2003-07-31 | 2004-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-29 | 2007-07-31 | 2008-01-30 | $7700.00 | Window Closed / Lapsed |