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US5488009A
Expired / Lapsed
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Post-titanium nitride mask ROM programming method
Assignee: United Microelectronics Corp
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Filing: 1994-11-23
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Granted: 1996-01-30
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Expires: 2014-11-23
Abstract
Abstract A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.
Inventors
- 👤 Chen-Chiu Hsue
- 👤 Yi-Chung Shen
- 👤 Shing-Ren Sheu
- 👤 Chen-Hui Chung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:49
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/38; H10B20/383; Y; Y10; Y10S; Y10S257/00; Y10S257/915
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
202 words
A method of manufacturing a ROM semiconductor device which comprises the steps in the sequential order of: taking a semiconductor substrate with an array of parallel burled bit lines integral therewith, laid buried bit lines being oriented in a first direction, a gate oxide lays: above said substrate and said buried bit lines, and word lines formed above said gate oxide layer, forming a dielectric layer over laid word lines and said gate oxide layer, forming a contact hole in said dielectric layer, forming a blanket titanium nitride layer over said device extending into said contact hole, forming a ROM code cask over said device, said ROM code mask having a ROR code opening therethrough, said opening being centered between a pair of said bit lines, performing etching of said titanium nitride layer through said ROM code mask, said titanium nitride layer having a stop height over said dielectric layer, ion implanting a code implant dopant through said ROM code opening down into a doped region in said substrate below said ROM code opening, removing said ROM code mask, performing a rapid thermal annealing step, applying a blanket layer of metal to said device including said contact hole, and patterning said metal.
Claim 2
Independent Claim
202 words
A method of manufacturing a ROM semiconductor device which comprises the steps in the sequential order of: taking a semiconductor substrate with an array of parallel burled bit lines integral therewith, laid buried bit lines being oriented in a first direction, a gate oxide lays: above said substrate and said buried bit lines, and word lines formed above said gate oxide layer, forming a dielectric layer over laid word lines and said gate oxide layer, forming a contact hole in said dielectric layer, forming a blanket titanium nitride layer over said device extending into said contact hole, forming a ROM code cask over said device, said ROM code mask having a ROR code opening therethrough, said opening being centered between a pair of said bit lines, performing etching of said titanium nitride layer through said ROM code mask, said titanium nitride layer having a stop height over said dielectric layer, ion implanting a code implant dopant through said ROM code opening down into a doped region in said substrate below said ROM code opening, removing said ROM code mask, performing a rapid thermal annealing step, applying a blanket layer of metal to said device including said contact hole, and patterning said metal.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein said dielectric layer comprises a boron phosphorous glass material.
Claim 4
Dependent Claim
21 words
The method of claim 1 wherein said dielectric has a thickness of within the range between about 2,000Å and about 4,000Å.
Claim 5
Dependent Claim
14 words
The method of claim 1 wherein said dielectric has a thickness of about 3,000Å.
Claim 6
Dependent Claim
19 words
The method of claim 1 wherein the step height is within the range between about 400Å and about 700Å.
Claim 7
Dependent Claim
12 words
The method of claim 3 wherein, the step height is about 500Å.
Claim 8
Dependent Claim
19 words
The method of claim 1 wherein the step height is within the range between about 400Å and about 700Å.
Claim 9
Dependent Claim
12 words
The method of claim 7 wherein, the step height is about 500Å.
Claim 10
Dependent Claim
23 words
The method of claim 3 wherein said rapid thermal annealing is performed within a range between about 650° C. and about 850° C.
Claim 11
Dependent Claim
16 words
The method of claim 9 wherein said rapid thermal annealing is performed at about 750° C.
Claim 12
Dependent Claim
23 words
The method of claim 3 wherein said rapid thermal annealing is performed within a range between about 650° C. and about 850° C.
Claim 13
Dependent Claim
16 words
The method of claim 11 wherein said rapid thermal annealing is performed at about 750° C.
Claim 14
Dependent Claim
17 words
The method of claim 12 wherein said dielectric layer comprises a material selected from BPSG and BPTEOS.
Claim 15
Independent Claim
194 words
A method of manufacturing a role semiconductor device which comprises the steps in the sequential order of: taking a semiconductor substrate with an array of parallel buried bit lines integral therewith, said buried bit lines being oriented in a first direction, a gate oxide layer above said substrate end said buried bit lines, and word lines formed above said gate oxide layer, forming a dielectric layer over said word lines, forming a contact hole in said dielectric layer, forming a blanket titanium nitride layer over said device extending into said contact hole, patterning said titanium nitride layer with a ROM code mask over said device, said ROM code mask having a ROM code opening therethrough, said ROM code opening being centered between a pair of said bit lines, performing a TiN etching through said code mask, ion implanting a code implant dopant through said ROM code opening down into a doped region in said substrate below said ROM code opening, removing said ROM code base, performing a rapid thermal annealing step after removing said ROM code mask, applying a blanket layer of metal to said device including said contact hole, and patterning said metal.
Claim 16
Independent Claim
194 words
A method of manufacturing a role semiconductor device which comprises the steps in the sequential order of: taking a semiconductor substrate with an array of parallel buried bit lines integral therewith, said buried bit lines being oriented in a first direction, a gate oxide layer above said substrate end said buried bit lines, and word lines formed above said gate oxide layer, forming a dielectric layer over said word lines, forming a contact hole in said dielectric layer, forming a blanket titanium nitride layer over said device extending into said contact hole, patterning said titanium nitride layer with a ROM code mask over said device, said ROM code mask having a ROM code opening therethrough, said ROM code opening being centered between a pair of said bit lines, performing a TiN etching through said code mask, ion implanting a code implant dopant through said ROM code opening down into a doped region in said substrate below said ROM code opening, removing said ROM code base, performing a rapid thermal annealing step after removing said ROM code mask, applying a blanket layer of metal to said device including said contact hole, and patterning said metal.
Claim 17
Dependent Claim
17 words
The method of claim 14 wherein said dielectric layer comprises a material selected from BPSG and BPTEOS.
Claim 18
Dependent Claim
25 words
The method of claim 14 wherein said dielectric has a thickness of within the range between about 2,000Å and about 4,000Å and preferably about 3,000Å.
Claim 19
Dependent Claim
23 words
The method of claim 16 wherein the step height is within the range between about 400Å and about 700Å and preferably about 500Å.
Claim 20
Dependent Claim
29 words
The method of claim 17 wherein said rapid thermal annealing is performed within a range between about 650° C. and about 850° C., and preferably at about 750° C.
Claim 21
Dependent Claim
17 words
The method of claim 18 wherein said dielectric layer comprises a material selected from BPSG and BPTEOS.
Claim 22
Dependent Claim
50 words
The method of claim 15 wherein the step height is within the range between about 400Å and about 700Å and preferably about 500Å, range between about 650° C. and about 850° C., and preferably at about 750° C., and said dielectric layer comprises a material selected from BPSG and BPTEOS.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-01-29 | 1999-07-31 | 2000-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-29 | 2003-07-31 | 2004-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-29 | 2007-07-31 | 2008-01-30 | $7700.00 | Window Closed / Lapsed |