US5484739A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a CMOS semiconductor device
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-12-08
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Granted: 1996-01-16
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Expires: 2014-12-08
Abstract
Abstract A semiconductor device and manufacturing method thereof is disclosed in which a connection pad layer for securing a contact margin is formed on a first conductivity-type area whereas electrodes are connected directly through openings on a second conductivity-type area without the connection pad layer. In the method, an insulating layer is formed on the overall surface of a substrate. Using a mask pattern for exposing the first conductivity-type area, the insulating layer placed on an exposed portion is anisotropically etched so that the remaining insulating layer serves as an impurity-implantation preventing mask in a succeeding first conductivity-type impurity implantation step. A material layer for the connection pad layer is formed prior to the impurity-implantation step and patterned after the impurity implantation. In forming the second conductivity-type area, an additional insulating layer is formed, and using a mask pattern for exposing the second conductivity area, selectively and anisotropically etched so that the remaining insulating layer or the mask pattern for exposing the second conductivity-type area serves as an impurity-implantation preventing mask.
Inventors
- 👤 Yong-hee Lee
- 👤 Young-woo Seo
- 👤 Jung-Hyun Shin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:40
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/05; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/013; H10D84/0135; H10D84/0147; H10D84/0149; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D84/8312; H10D84/835; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
197 words
A method of manufacturing a semiconductor device including at least one first conductivity-type area and at least one second conductivity-type area, said method comprising the steps of: forming an insulating layer on a semiconductor substrate in which portions for forming said first and second conductivity-type areas are defined; forming a first mask pattern for exposing the portion for forming said first conductivity-type area and covering the portion for forming said second conductivity-type area; anisotropically etching said insulating layer formed on the exposed portion according to the geometric characteristics of said semiconductor substrate; removing said first mask pattern; forming a first material layer for forming a connection pad layer on the overall surface of the resultant structure; implanting a first conductivity-type impurity by using said insulating layer remaining under said first material layer as an impurity implantation preventing mask; patterning said first material layer and forming said connection pad layer on said first conductivity-type area; forming a second mask pattern for exposing the portion for forming said second conductivity-type area and blocking the portion for forming said first conductivity-type area; and implanting a second conductivity-type impurity by using said second mask pattern as an impurity implantation preventing mask.
Claim 2
Independent Claim
197 words
A method of manufacturing a semiconductor device including at least one first conductivity-type area and at least one second conductivity-type area, said method comprising the steps of: forming an insulating layer on a semiconductor substrate in which portions for forming said first and second conductivity-type areas are defined; forming a first mask pattern for exposing the portion for forming said first conductivity-type area and covering the portion for forming said second conductivity-type area; anisotropically etching said insulating layer formed on the exposed portion according to the geometric characteristics of said semiconductor substrate; removing said first mask pattern; forming a first material layer for forming a connection pad layer on the overall surface of the resultant structure; implanting a first conductivity-type impurity by using said insulating layer remaining under said first material layer as an impurity implantation preventing mask; patterning said first material layer and forming said connection pad layer on said first conductivity-type area; forming a second mask pattern for exposing the portion for forming said second conductivity-type area and blocking the portion for forming said first conductivity-type area; and implanting a second conductivity-type impurity by using said second mask pattern as an impurity implantation preventing mask.
Claim 3
Dependent Claim
49 words
A method of manufacturing a semiconductor device as claimed in claim 1, further comprising, prior to said step of implanting said second conductivity-type impurity, the stop of anisotropically etching said insulating layer formed on the portion exposed by said second-mask pattern according to geometric characteristics of said semiconductor substrate.
Claim 4
Dependent Claim
63 words
A method of manufacturing a semiconductor device as claimed in claim 1, further comprising, after said step of implanting said second conductivity-type impurity, the steps of: removing said second mask pattern; and forming an interlevel dielectric layer having a plurality of openings for exposing the portions of said connection pad layer and second conductivity-type area on the overall surface of said resultant structure.
Claim 5
Dependent Claim
32 words
A method of manufacturing a semiconductor device as claimed in claim 1, wherein said step of forming said first material layer as the connection pad layer is a step of depositing polysilicon.
Claim 6
Dependent Claim
125 words
A method of manufacturing a semiconductor device as claimed in claim 1, further comprising, prior to said step of forming said insulating layer, the steps of: selectively defining an active area and device isolation area on said semiconductor substrate; forming a gate insulating layer on the resultant structure; sequentially forming a second material layer and cap insulating layer for gate electrode on said gate insulating layer; forming a gate-mask pattern for defining said gate electrode on the resultant structure; and sequentially and selectively etching said cap insulating layer, second material layer and gate insulating layer by using said gate-mask pattern as an etching preventing mask, wherein spacers are formed on the sidewalls of respective gate electrodes through said step of anisotropically etching said insulating layer.
Claim 7
Dependent Claim
48 words
A method of manufacturing a semiconductor device as claimed in claim 5, further comprising, prior to said step of forming said insulating layer, the step of doping a first conductivity-type impurity on said semiconductor substrate in which portions for forming said first and second conductivity-type areas are defined.
Claim 8
Independent Claim
224 words
A method of manufacturing a semiconductor device including at least one first conductivity-type area and at least one second conductivity-type area, said method comprising the steps of: forming an insulating layer on a semiconductor substrate in which portions for forming said first and second conductivity-type areas are defined; forming a first mask pattern for exposing the portion for forming said second conductivity-type area and covering the portion for forming said first conductivity-type area; anisotropically etching said insulating layer according to the geometric characteristics of the substructure of said layer by using said second mask pattern; removing said first mask pattern; implanting a second conductivity-type impurity by using said etched insulating layer as an impurity implantation preventing mask; forming a second mask pattern for exposing the portion for forming said first conductivity-type area and covering the portion for forming said second conductivity-type area; anisotropically etching said insulating layer formed on the exposed portion according to the geometric characteristics of said semiconductor substrate; removing said second mask pattern; forming a first material layer for forming a connection pad layer on the overall surface of the resultant structure; implanting a first conductivity-type impurity by using said insulating layer left under said first material layer as an impurity implantation preventing mask; and patterning said first material layer and forming said connection pad layer on said first conductivity-type area.
Claim 9
Independent Claim
224 words
A method of manufacturing a semiconductor device including at least one first conductivity-type area and at least one second conductivity-type area, said method comprising the steps of: forming an insulating layer on a semiconductor substrate in which portions for forming said first and second conductivity-type areas are defined; forming a first mask pattern for exposing the portion for forming said second conductivity-type area and covering the portion for forming said first conductivity-type area; anisotropically etching said insulating layer according to the geometric characteristics of the substructure of said layer by using said second mask pattern; removing said first mask pattern; implanting a second conductivity-type impurity by using said etched insulating layer as an impurity implantation preventing mask; forming a second mask pattern for exposing the portion for forming said first conductivity-type area and covering the portion for forming said second conductivity-type area; anisotropically etching said insulating layer formed on the exposed portion according to the geometric characteristics of said semiconductor substrate; removing said second mask pattern; forming a first material layer for forming a connection pad layer on the overall surface of the resultant structure; implanting a first conductivity-type impurity by using said insulating layer left under said first material layer as an impurity implantation preventing mask; and patterning said first material layer and forming said connection pad layer on said first conductivity-type area.
Claim 10
Dependent Claim
54 words
A method of manufacturing a semiconductor device as claimed in claim 7, further comprising, after said step of forming said connection pad layer, the step of forming an interlevel dielectric layer having a plurality of openings for exposing said connection pad layer and second conductivity-type area on the overall surface of the resultant structure.
Claim 11
Dependent Claim
19 words
A method of manufacturing a semiconductor device as claimed in claim 7, wherein said first material layer is polysilicon.
Claim 12
Dependent Claim
126 words
A method of manufacturing a semiconductor device as claimed in claim 7, further comprising, prior to said step of forming said first insulating layer, the steps of: selectively defining an active area and device isolation area on said semiconductor substrate; forming a gate insulating layer on the resultant structure; sequentially forming a second material layer and cap insulating layer for gate electrode on said gate insulating layer; forming a gate-mask pattern for defining said gate electrode on the resultant structure; and sequentially and selectively etching said cap insulating layer, second material layer and gate insulating layer by using said gate-mask pattern as an etching preventing mask, wherein spacers are formed on the sidewalls of respective gate electrodes through said step of anisotropically etching said insulating layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-15 | 1999-07-17 | 2000-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-15 | 2003-07-17 | 2004-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-15 | 2007-07-17 | 2008-01-16 | $7700.00 | Window Closed / Lapsed |