Patent US4586625A successfully refreshed from Google Patents.
US5483496A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Nonvolatile memory device having a timer circuit
Assignee: Seiko Instruments Inc
•
Filing: 1994-04-18
•
Granted: 1996-01-09
•
Expires: 2014-04-18
Abstract
Abstract When execution of a program is interrupted during erasure or writing, electric charge normally remains due to high voltage. This charge is electrically discharged to thereby prevent erroneous erasure, erroneous writing, and erroneous reading. It comprises a timer circuit for producing a shortened program timing pulse when execution of a program is interrupted, together with a word line driver, a control line driver, and a bit line driver which are controlled by the timer circuit. A program-interrupting signal 30 is applied to a selector 23 which then switches the connected clock-generating circuit from a clock-generating circuit 21 to a clock-generating circuit 22 of a higher clock frequency in response to the signal 30. Therefore, when the execution of the program is interrupted, the shortened program timing pulse for interruption is applied to each memory cell. When execution of a program is interrupted during erasure or writing, erroneous erasure, erroneous writing, and erroneous reading can be prevented.
Inventors
- 👤 Kazuhiko Murakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:24
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3427
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
111 words
A nonvolatile memory device having electrically erasable nonvolatile memory cells, and a timer circuit for producing normal program timing pulses for executing a program to the electrically erasable nonvolatile memory cells, wherein the timer circuit provides a shortened program timing pulse for the electrically erasable nonvolatile memory cells in response to an external-interrupting signal provided to the timer circuit during interruption of the program, a cycle of the shortened program timing pulse being shorter than that of the normal program timing pulses during normal execution of the program so that the program is ended after discharging electric charges in the electrically erasable nonvolatile memory cells by the shortened program timing pulse.
Claim 2
Dependent Claim
111 words
A nonvolatile memory device having electrically erasable nonvolatile memory cells, and a timer circuit for producing normal program timing pulses for executing a program to the electrically erasable nonvolatile memory cells, wherein the timer circuit provides a shortened program timing pulse for the electrically erasable nonvolatile memory cells in response to an external-interrupting signal provided to the timer circuit during interruption of the program, a cycle of the shortened program timing pulse being shorter than that of the normal program timing pulses during normal execution of the program so that the program is ended after discharging electric charges in the electrically erasable nonvolatile memory cells by the shortened program timing pulse.
Claim 3
Dependent Claim
85 words
A nonvolatile memory device according to claim 1, wherein the timer circuit comprises a selector for providing the program timing pulses to the electrically erasable nonvolatile memory cells, a first decoder circuit for providing the program timing pulses to the selector, and a second decoder circuit for providing the shortened program timing pulse to the selector, wherein the selector selects the shortened program timing pulse as an output to the electrically erasable nonvolatile memory cells in response to the external-interrupting signal applied to the selector.
Claim 4
Dependent Claim
114 words
A nonvolatile memory device according to claim 1, wherein the timer circuit comprises a decoder circuit for providing the program timing pulses to the electrically erasable nonvolatile memory cells, a selector for providing timing pulses to the decoder circuit, a first counter circuit for providing first timing pulses to the selector, and a second counter circuit for providing a second timing pulse which is shorter than the first timing pulses to the selector, wherein the selector selects the second timing pulse as an output to the decoder in response to the external-interrupting signal applied to the selector so that the decoder provides the shortened program timing pulse to the electrically erasable nonvolatile memory cells.
Claim 5
Dependent Claim
126 words
A nonvolatile memory device according to claim 1, wherein the timer circuit comprises a decoder circuit for providing the program timing pulses to the electrically erasable nonvolatile memory cells, a counter circuit for providing timing pulses to the decoder circuit, a selector for providing clock pulses to the counter circuit, a first clock-generating circuit for providing first clock pulses to the selector, and a second clock-generating circuit for providing a second clock pulse which is shorter than the first clock pulses to the selector, wherein the selector selects the second clock pulse as an output to the counter circuit in response to the external-interrupting signal applied to the selector so that the decoder provides the shortened program timing pulse to the electrically erasable nonvolatile memory cells.
Claim 6
Dependent Claim
107 words
A nonvolatile memory device according to claim 1, wherein the timer circuit comprises a decoder circuit for providing the program timing pulses to the electrically erasable nonvolatile memory cells, a counter circuit for providing timing pulses to the decoder circuit, and a clock-generating circuit for providing clock pulses to the counter circuit, wherein the clock-generating circuit provides a shorter cycle of the clock pulses in response to the external-interrupting signal applied to the clock-generating circuit than a cycle of the clock pulse during normal program, so that the decoder provides the shortened program timing pulse to the electrically erasable nonvolatile memory cells coupled with the external-interrupting signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |