US5483093A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input protection device for electronic device
Assignee: Nissan Motor Co Ltd
•
Filing: 1993-12-06
•
Granted: 1996-01-09
•
Expires: 2013-12-06
Abstract
Abstract An input protection device comprises a current limiting resistor externally connected to an integrated circuit which includes two Zener diodes, one functioning as a power supply Zener diode and the other functioning as a ground Zener diode. Owing to the resistance of the current limiting resistor and junction capacitances of the Zener diodes, electromagnetic interference noise is effectively damped or attenuated.
Inventors
- 👤 Koichi Murakami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:08
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
372 words
In an input protection device adapted to be connected between a switch and an electronic device and circuited between a power supply and ground, the input protection device including a current limiting resistor having one end connected to the switch and an opposite end: a semiconductor substrate (170) of one conductive type, said semiconductor substrate having a surface; a first well region (151) extending into said semiconductor substrate from said surface and forming a first PN junction with the surrounding portions of said semiconductor substrate; a second region (152) of the same type as and of higher impurity concentration than the remainder of said first well region (151) extending into said surface within said first well region (151); a third region (153) of the same type as and of higher impurity concentration than the remainder of said semiconductor substrate extending into said surface within said first well region (151) and forming a second PN junction with said second region (152); a fourth region (154) of the same type as and of higher impurity concentration than the remainder of said first well region (151) extending into said surface at one end of said first well region and forming a third PN junction with the portions of said semiconductor substrate adjacent said first well region a fifth well region (161) extending into said semiconductor substrate from said surface and forming a fourth PN junction with the surrounding portions of said semiconductor substrate (170); a sixth region (162) of the same type as and of higher impurity concentration than the remainder of said fifth well region (161) extending into said surface within said fifth well region a seventh region (163) of the same type as and of higher impurity concentration than the remainder of said semiconductor substrate (170) extending into said surface within said fifth well region (161) and forming a fifth PN junction with said sixth region (162); and an eighth region (164) of the same type as and of higher impurity concentration than the remainder of said fifth well region (161) extending into said surface at one end of said fifth well region and forming a sixth PN junction with the portions of said semiconductor substrate (170) adjacent said fifth well region (161).
Claim 2
Dependent Claim
372 words
In an input protection device adapted to be connected between a switch and an electronic device and circuited between a power supply and ground, the input protection device including a current limiting resistor having one end connected to the switch and an opposite end: a semiconductor substrate (170) of one conductive type, said semiconductor substrate having a surface; a first well region (151) extending into said semiconductor substrate from said surface and forming a first PN junction with the surrounding portions of said semiconductor substrate; a second region (152) of the same type as and of higher impurity concentration than the remainder of said first well region (151) extending into said surface within said first well region (151); a third region (153) of the same type as and of higher impurity concentration than the remainder of said semiconductor substrate extending into said surface within said first well region (151) and forming a second PN junction with said second region (152); a fourth region (154) of the same type as and of higher impurity concentration than the remainder of said first well region (151) extending into said surface at one end of said first well region and forming a third PN junction with the portions of said semiconductor substrate adjacent said first well region a fifth well region (161) extending into said semiconductor substrate from said surface and forming a fourth PN junction with the surrounding portions of said semiconductor substrate (170); a sixth region (162) of the same type as and of higher impurity concentration than the remainder of said fifth well region (161) extending into said surface within said fifth well region a seventh region (163) of the same type as and of higher impurity concentration than the remainder of said semiconductor substrate (170) extending into said surface within said fifth well region (161) and forming a fifth PN junction with said sixth region (162); and an eighth region (164) of the same type as and of higher impurity concentration than the remainder of said fifth well region (161) extending into said surface at one end of said fifth well region and forming a sixth PN junction with the portions of said semiconductor substrate (170) adjacent said fifth well region (161).
Claim 3
Dependent Claim
105 words
An input protection device as set forth in claim 1, wherein when said third region (153) is connected to the power supply (V DD ), said fourth region (154) is connected to the opposite end of the to current limiting resistor, said seventh region (163) is connected to the opposite end of the current limiting resistor, and said eighth region (164) is connected to the ground, said second PN junction formed by said second and third regions (152, 153) and said fifth PN junction formed by said sixth and seventh regions (162, 163) serve as a power supply Zener diode and a ground Zener diode.
References Cited (Backward Citations)
US4254442A
Cited
JPS61100954A
Cited
US4761566A
Cited
JPS6281048A
Cited
JPS63260160A
Cited
JPH022202A
Cited
US5014155A
Cited
US5027181A
Cited
US5223737A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-08 | 1999-07-10 | 2000-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-08 | 2003-07-10 | 2004-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-08 | 2007-07-10 | 2008-01-09 | $7700.00 | Window Closed / Lapsed |