Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
321 words
A Direct Memory Access (DMA) controller comprising: a transfer size register written, before a first series of DMA transfer operations being executed are completed, with the number of DMA transfer operations to be performed in a second series of DMA transfer operations to be executed after said first series of DMA transfer operations are executed; a transfer destination address register written, before said first series of DMA transfer operations being executed are completed, with a transfer destination head address for said second series of DMA transfer operations to be executed after said first series of DMA transfer operations are executed; a control unit configured to start a DMA transfer for said second series of DMA transfer operations by using values of the number of DMA transfer operations and the transfer destination head address respectively written in said transfer size register and said transfer destination address register and to generate a transfer completion status signal, when the DMA transfer for said first series of DMA transfer operations has been completed, said control unit being also configured to generate an auto-initialize halt operation setting signal indicating that an auto-initialize operation halting mode is set, and a register write confirmation status signal indicating that a new set value is written into either or both of said transfer size register and said transfer destination address register during execution of the DMA transfer for said first series of DMA transfer operations; an auto-initialize operation completion discriminator, receiving said transfer completion status signal, said auto-initialize halt operation setting signal and said register write confirmation status signal, for generating a halt request signal when all of said transfer completion status signal, said auto-initialize halt operation setting signal and said register write confirmation status signal are active; and an auto-initialize operation halting unit responding to said halt request signal so as to halt an auto-initialize operation and to generate a signal indicating that the auto-initialize operation has been halted.
Claim 2
Dependent Claim
321 words
A Direct Memory Access (DMA) controller comprising: a transfer size register written, before a first series of DMA transfer operations being executed are completed, with the number of DMA transfer operations to be performed in a second series of DMA transfer operations to be executed after said first series of DMA transfer operations are executed; a transfer destination address register written, before said first series of DMA transfer operations being executed are completed, with a transfer destination head address for said second series of DMA transfer operations to be executed after said first series of DMA transfer operations are executed; a control unit configured to start a DMA transfer for said second series of DMA transfer operations by using values of the number of DMA transfer operations and the transfer destination head address respectively written in said transfer size register and said transfer destination address register and to generate a transfer completion status signal, when the DMA transfer for said first series of DMA transfer operations has been completed, said control unit being also configured to generate an auto-initialize halt operation setting signal indicating that an auto-initialize operation halting mode is set, and a register write confirmation status signal indicating that a new set value is written into either or both of said transfer size register and said transfer destination address register during execution of the DMA transfer for said first series of DMA transfer operations; an auto-initialize operation completion discriminator, receiving said transfer completion status signal, said auto-initialize halt operation setting signal and said register write confirmation status signal, for generating a halt request signal when all of said transfer completion status signal, said auto-initialize halt operation setting signal and said register write confirmation status signal are active; and an auto-initialize operation halting unit responding to said halt request signal so as to halt an auto-initialize operation and to generate a signal indicating that the auto-initialize operation has been halted.
Claim 3
Dependent Claim
147 words
A DMA controller claimed in claim 1 further including: a transfer size counter loaded with a content of said transfer size register when said control unit starts one of the DMA transfer for said first series of DMA transfer operations and the DMA transfer for said second series of DMA transfer operations, said transfer size counter being updated at each time one DMA transfer operation is performed during execution of a series of DMA transfer operations; and a transfer destination address counter loaded with a content of said transfer destination address register when said control unit starts one of the DMA transfer for said first series of DMA transfer operations and the DMA transfer for said second series of DMA transfer operations, said transfer destination address counter being updated at each time one DMA transfer operation is performed during execution of the series of DMA transfer operations.
Claim 4
Dependent Claim
76 words
A DMA controller claimed in claim 1 further including: a transfer size counter loaded with a content of said transfer size register when said control unit starts one of the DMA transfer for said first series of DMA transfer operations and the DMA transfer for said second series of DMA transfer operations, said transfer size counter being updated at each time one DMA transfer operation is performed during execution of a series of DMA transfer operations.
Claim 5
Dependent Claim
79 words
A DMA controller claimed in claim 1 further including: a transfer destination address counter loaded with a content of said transfer destination address register when said control unit starts one of the DMA transfer for said first series of DMA transfer operations and the DMA transfer for said second series of DMA transfer operations, said transfer destination address counter being updated at each time one DMA transfer operation is performed during execution of a series of DMA transfer operations.