I/O module with reduced isolation circuitry

Claim 1

An I/O module comprising: an isolation interface that includes a first signal path for a clock signal and a second signal path for serial data; a first programmable logic circuit which is programmable in response to configuration data to emulate functions for a plurality of digital circuits, the first programmable logic circuit including first means electrically connected to the first and second signal paths for transfer of configuration data during configuration operations and including second means electrically connected to the first and second signal paths for transfer of other data during post-configuration operations; a second programmable logic circuit which is programmable in response to configuration data to emulate functions for a plurality of digital circuits, the second programmable logic circuit being coupled through the isolation interface to the first programmable logic circuit, to receive system I/O data to monitor and control I/O devices and connected, during the operation of the I/O module, to I/O devices on a controlled machine or process to monitor and control the I/O devices in accordance with the system I/O data, the second programmable logic circuit including first means electrically connected to the first and second signal paths for receiving configuration data during configuration operations, the configuration data programming the second programmable logic circuit to reduce the amount of system I/O data that must be transferred across the isolation interface and including second means electrically connected to the first and second signal paths for receiving other data during post-configuration operations wherein the second programmable logic circuit includes means for generating output signals for controlling motion and also includes means for receiving feedback signals from the I/O devices; a memory that stores first instructions for transfer of data during configuration operations and second instructions for transfer of data during post-configuration operations; a microprocessor responsive to the first instructions in the memory for transferring configuration data to the first programmable logic circuit during configuration operations; the microprocessor being responsive to the second instructions in the memory to transfer data to the first programmable logic circuit during post-configuration operations.