US5479124A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Slew rate controller for high speed bus
Assignee: GlobalFoundries Inc
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Filing: 1993-08-20
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Granted: 1995-12-26
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Expires: 2013-08-20
Abstract
Abstract A technique for high speed transmission of digital signals on a bus line with reduced signal ringing, bounce and bus contention current. The approach uses a multi-partitioned driver design with temporary and steady state parts incorporating internal feedback and delay techniques to control the output slew rate. A built-in function outputs the driving status of the transceiver and allows the output to enter the high impedance status asynchronously.
Inventors
- 👤 Philip Y. Pun
- 👤 William A. Stutz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:40
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
145 words
In an integrated circuit, an apparatus for transmitting and receiving digital signals through a connector for connection with a signal line comprising: a first driver circuit coupled to said connector capable of providing sink or source current to move a voltage level on said signal line to a desired voltage when said connector is connected to said signal line; a second driver circuit coupled to said connector capable of providing sink or source current to maintain a desired voltage level on said signal line when said connector is connected to said signal line; an input latch coupled to said connector capable of latching data in response to a timing signal; and timing circuitry coupled to said first driver circuit, said second driver circuit, and said input latch for independently turning-on and turning-off said first and said second driver circuits, and for controlling said input latch.
Claim 2
Dependent Claim
145 words
In an integrated circuit, an apparatus for transmitting and receiving digital signals through a connector for connection with a signal line comprising: a first driver circuit coupled to said connector capable of providing sink or source current to move a voltage level on said signal line to a desired voltage when said connector is connected to said signal line; a second driver circuit coupled to said connector capable of providing sink or source current to maintain a desired voltage level on said signal line when said connector is connected to said signal line; an input latch coupled to said connector capable of latching data in response to a timing signal; and timing circuitry coupled to said first driver circuit, said second driver circuit, and said input latch for independently turning-on and turning-off said first and said second driver circuits, and for controlling said input latch.
Claim 3
Dependent Claim
19 words
The apparatus of claim 1 wherein said first driver circuit includes a means for internal feedback slew rate control.
Claim 4
Dependent Claim
104 words
The apparatus of claim 1 wherein said first driver circuit comprises: a first pull up sequentially gated transistor bank coupled to said connector; a second pull up sequentially gated transistor bank with internal feedback slew rate control coupled to said connector; a first pull down sequentially gated transistor bank coupled to said connector; a second pull down sequentially gated transistor bank with internal feedback slew rate control coupled to said connector; and control circuitry coupled to said pull up and pull down transistors for turning on either said pull up or said pull down transistors in response to a data signal and timing signals.
Claim 5
Dependent Claim
56 words
The apparatus of claim 1, further comprising: a STAT signal coupled to said second driver circuit for indicating whether said second driver circuit is driving said signal line; and a SYNC signal coupled to said first driver circuit and said second driver circuit for asynchronously turning off said first driver circuit and said second driver circuit.
Claim 6
Independent Claim
134 words
A method for transmitting data between a plurality of data processing circuits on a signal line comprising: enabling one of said data processing circuits to transmit data during the first part of a data clock cycle with a first driver circuit coupled to said signal line capable of providing sink or source current to move a voltage level on said signal line to a desired voltage; enabling said one of said data processing circuits to transmit data during the first and second parts of a data cycle with a second driver circuit coupled to said signal line capable of maintaining a desired voltage level on said signal line; latching the data at each of said data processing circuits with an input latch coupled to said signal line at the end of said data cycle.
Claim 7
Independent Claim
134 words
A method for transmitting data between a plurality of data processing circuits on a signal line comprising: enabling one of said data processing circuits to transmit data during the first part of a data clock cycle with a first driver circuit coupled to said signal line capable of providing sink or source current to move a voltage level on said signal line to a desired voltage; enabling said one of said data processing circuits to transmit data during the first and second parts of a data cycle with a second driver circuit coupled to said signal line capable of maintaining a desired voltage level on said signal line; latching the data at each of said data processing circuits with an input latch coupled to said signal line at the end of said data cycle.
Claim 8
Independent Claim
161 words
An apparatus for communicating digital signals on a signal line between a transmitting data processing circuit and a receiving data processing circuit comprising: a first driver circuit operatively connected to said transmitting data processing circuit and coupled to said signal line capable of providing sink or source current to move a voltage level on said signal line to a desired voltage; a second driver circuit operatively connected to said transmitting data processing circuit and coupled to said signal line capable of providing sink or source current to maintain a desired voltage level on said signal line; an input latch operatively connected to said receiving data processing circuit and coupled to said signal line capable of latching data on said signal line in response to a timing signal; and timing circuitry coupled to said first driver circuit, said second driver circuit, and said input latch for controlling said latch and for turning-on and turning-off of said first and said second driver circuits.
Claim 9
Independent Claim
161 words
An apparatus for communicating digital signals on a signal line between a transmitting data processing circuit and a receiving data processing circuit comprising: a first driver circuit operatively connected to said transmitting data processing circuit and coupled to said signal line capable of providing sink or source current to move a voltage level on said signal line to a desired voltage; a second driver circuit operatively connected to said transmitting data processing circuit and coupled to said signal line capable of providing sink or source current to maintain a desired voltage level on said signal line; an input latch operatively connected to said receiving data processing circuit and coupled to said signal line capable of latching data on said signal line in response to a timing signal; and timing circuitry coupled to said first driver circuit, said second driver circuit, and said input latch for controlling said latch and for turning-on and turning-off of said first and said second driver circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-25 | 1999-06-26 | 1999-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-25 | 2003-06-26 | 2003-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-25 | 2007-06-26 | 2007-12-26 | $7700.00 | Window Closed / Lapsed |