Fieldless split-gate EPROM/Flash EPROM

Claim 2

A self-aligned, split-gate EPROM/Flash EPROM array device, comprising: a) a doped well in a semiconductor substrate of said device containing buried bit lines, b) a dielectric layer on the surface of said doped well with a thick dielectric over said implanted ions, c) a threshold voltage dopant in said doped well, d) first polysilicon floating gates on said silicon dioxide layer, e) an inter polysilicon layer on the surface of said first polysilicon structures f) a second polysilicon layer on said inter polysilicon layer in the form of word lines extending orthogonally to said buried bit lines and extending across said floating gates, and g) a trough extending down into said well in the space defined within said buried bit lines and said second polysilicon layer, h) dielectric structures on the sides of said gate and said word lines, i) an isolation implant in said trough, and j) a dielectric layer on said trough, k) dielectric structures on the sides of said gate and said word lines, l) an isolation implant area in said trough, and m) a dielectric layer on said trough.

Claim 3

A device in accordance with claim 1 wherein said isolation implant area comprises boron ions within the range of from about 5×10 12 /cm 2 to about 2×10 13 /cm 2 implanted at about 30 keV.

Claim 4

A device in accordance with claim 2 wherein said trough is about 3000Å deep.

Claim 5

A self-aligned, split-gate EPROM/Flash EPROM array device, manufactured by the process comprising the following steps: a) implanting ions into predetermined locations in a doped well in a semiconductor substrate of said device to form buried bit lines, b) forming a dielectric layer on the surface of said doped well forming a thick dielectric over said implanted ions, c) implanting a first threshold voltage V T1 dopant into said doped well, d) formation of a first polysilicon layer on said silicon dioxide layer, e) forming an inter polysilicon layer on the surface of said first polysilicon layer on said device, f) patterning said first polysilicon layer by forming a mask with openings and etching said polysilicon through said openings in said mask, g) formation of a second polysilicon layer on said inter polysilicon layer, h) forming a photolithographic mask and etching portions of said second polysilicon layer to form word lines therein, and etching portions of said first polysilicon layer and said inter polysilicon dielectric to form a stacked gate beneath said word lines with a trough etched down into said well in the space defined within said buried bit lines and said second polysilicon layer, and i) implanting an isolation implant into said trough, whereby preliminary manufacture of said device is completed.

Claim 6

A self-aligned, split-gate EPROM/Flash EPROM array device, manufactured by the process comprising the following steps: a) implanting ions into predetermined locations in a doped well in a semiconductor substrate of said device to form buried bit lines, b) forming a dielectric layer on the surface of said doped well forming a thick dielectric over said implanted ions, c) implanting a first threshold voltage V T1 dopant into said doped well, d) formation of a first polysilicon layer on said silicon dioxide layer, e) forming an inter polysilicon layer on the surface of said first polysilicon layer on said device, f) patterning said first polysilicon layer by forming a mask with openings and etching said polysilicon through said openings in said mask, g) formation of a second polysilicon layer on said inter polysilicon layer, h) forming a photolithographic mask and etching portions of said second polysilicon layer to form word lines therein, and etching portions of said first polysilicon layer and said inter polysilicon dielectric to form a stacked gate beneath said word lines with a trough etched down into said well in the space defined within said buried bit lines and said second polysilicon layer, and i) implanting an isolation implant into said trough, whereby preliminary manufacture of said device is completed.

Claim 7

A self-aligned, split-gate EPROM/Flash EPROM array device, manufactured by the process comprising the following steps: a) ions implanted into predetermined locations in a doped well in a semiconductor substrate of said device forming buried bit lines, b) a dielectric layer on the surface of said doped well comprising a thick dielectric over said implanted ions, c) a first threshold voltage V T1 dopant ion implanted into said doped well, d) a first polysilicon layer on said silicon dioxide layer, e) an inter polysilicon layer on the surface of said first polysilicon layer on said device, f) said first polysilicon layer patterned with openings etched through said polysilicon, g) a second polysilicon layer on said inter polysilicon layer, h) said second polysilicon layer patterned in the form of word lines, and portions of said first polysilicon layer and said inter polysilicon dielectric patterned in the form a stacked gate beneath said word lines with a trough etched down into said well in the space defined within said buried bit lines and said second polysilicon layer, and i) an isolation area ion implanted into said trough.

Claim 8

A self-aligned, split-gate EPROM/Flash EPROM array device, manufactured by the process comprising the following steps: a) ions implanted into predetermined locations in a doped well in a semiconductor substrate of said device forming buried bit lines, b) a dielectric layer on the surface of said doped well comprising a thick dielectric over said implanted ions, c) a first threshold voltage V T1 dopant ion implanted into said doped well, d) a first polysilicon layer on said silicon dioxide layer, e) an inter polysilicon layer on the surface of said first polysilicon layer on said device, f) said first polysilicon layer patterned with openings etched through said polysilicon, g) a second polysilicon layer on said inter polysilicon layer, h) said second polysilicon layer patterned in the form of word lines, and portions of said first polysilicon layer and said inter polysilicon dielectric patterned in the form a stacked gate beneath said word lines with a trough etched down into said well in the space defined within said buried bit lines and said second polysilicon layer, and i) an isolation area ion implanted into said trough.

Claim 9

A device in accordance with claim 5 wherein said isolation implant area comprises boron ions within the range of from about 5×10 12 /cm 2 to about 2×10 13 /cm 2 implanted at about 30 keV.

Claim 10

A device in accordance with claim 6 wherein said trough is about 3000Å deep.

Claim 11

A device in accordance with claim 7 wherein dielectric structures are formed on the sides of said gate and said word lines.

Claim 12

A device in accordance with claim 8 wherein a dielectric layer is formed on said trough.

Claim 13

A self-aligned, split-gate EPROM/Flash EPROM array device manufactured by the process comprising the following steps: a) implanting ions into predetermined locations in a doped well in a semiconductor substrate of said device to form buried bit lines, b) forming a silicon dioxide layer on the surface of said doped well forming thicker oxide over said implanted ions, c) implanting a first threshold voltage V T1 dopant into said doped well, d) formation of a first polysilicon layer on said silicon dioxide layer, e) forming an inter polysilicon layer on the surface of said first polysilicon layer on said device, f) patterning said first polysilicon layer by forming a mask with openings and etching said polysilicon through said openings in said mask, g) implanting a second threshold voltage V T2 dopant into said doped well, h) removal of the exposed portions of said silicon dioxide layer exposing the surface of said doped well, i) forming a second silicon dioxide layer on the exposed surface of said doped well, j) formation of a second polysilicon layer on said inter polysilicon layer, k) forming a photolithographic mask and etching portions of said second polysilicon layer to form word lines therein, and etching portions of said first polysilicon layer and said inter polysilicon dielectric to form a stacked gate beneath said word lines with a trough etched down into said well in the space defined within said buried bit lines and said second polysilicon layer, and l) implanting an isolation implant into said trough, whereby preliminary manufacture of said device is completed.

Claim 14

A self-aligned, split-gate EPROM/Flash EPROM array device manufactured by the process comprising the following steps: a) implanting ions into predetermined locations in a doped well in a semiconductor substrate of said device to form buried bit lines, b) forming a silicon dioxide layer on the surface of said doped well forming thicker oxide over said implanted ions, c) implanting a first threshold voltage V T1 dopant into said doped well, d) formation of a first polysilicon layer on said silicon dioxide layer, e) forming an inter polysilicon layer on the surface of said first polysilicon layer on said device, f) patterning said first polysilicon layer by forming a mask with openings and etching said polysilicon through said openings in said mask, g) implanting a second threshold voltage V T2 dopant into said doped well, h) removal of the exposed portions of said silicon dioxide layer exposing the surface of said doped well, i) forming a second silicon dioxide layer on the exposed surface of said doped well, j) formation of a second polysilicon layer on said inter polysilicon layer, k) forming a photolithographic mask and etching portions of said second polysilicon layer to form word lines therein, and etching portions of said first polysilicon layer and said inter polysilicon dielectric to form a stacked gate beneath said word lines with a trough etched down into said well in the space defined within said buried bit lines and said second polysilicon layer, and l) implanting an isolation implant into said trough, whereby preliminary manufacture of said device is completed.

Claim 15

A self-aligned, split-gate EPROM/Flash EPROM array device comprising a) ions implanted into predetermined locations in a doped well in a semiconductor substrate of said device in the form of buried bit lines, b) a silicon dioxide layer on the surface of said doped well forming thicker oxide over said implanted ions, c) a first threshold voltage V T1 dopant implanted into said doped well, d) a first polysilicon layer formed on said silicon dioxide layer patterned mask with openings etched through said first polysilicon layer, e) an inter dielectric polysilicon layer formed on the surface of said first polysilicon layer on said device, f) a second threshold voltage V T2 dopant implanted into said doped well, g) openings in said silicon dioxide layer exposing the surface of said doped well with a second silicon dioxide layer formed on the surface of said doped well exposed through said openings in said silicon dioxide layer, h) a second polysilicon layer formed on said inter polysilicon layer, k) said second polysilicon layer patterned in the form of word lines therein, and portions of said first polysilicon layer and said inter polysilicon dielectric layer etched to form a stacked gate beneath said word lines with a trough etched down into said well in the space defined within said buried bit lines and said second polysilicon layer, and l) an isolation area implanted into said trough.

Claim 16

A self-aligned, split-gate EPROM/Flash EPROM array device comprising a) ions implanted into predetermined locations in a doped well in a semiconductor substrate of said device in the form of buried bit lines, b) a silicon dioxide layer on the surface of said doped well forming thicker oxide over said implanted ions, c) a first threshold voltage V T1 dopant implanted into said doped well, d) a first polysilicon layer formed on said silicon dioxide layer patterned mask with openings etched through said first polysilicon layer, e) an inter dielectric polysilicon layer formed on the surface of said first polysilicon layer on said device, f) a second threshold voltage V T2 dopant implanted into said doped well, g) openings in said silicon dioxide layer exposing the surface of said doped well with a second silicon dioxide layer formed on the surface of said doped well exposed through said openings in said silicon dioxide layer, h) a second polysilicon layer formed on said inter polysilicon layer, k) said second polysilicon layer patterned in the form of word lines therein, and portions of said first polysilicon layer and said inter polysilicon dielectric layer etched to form a stacked gate beneath said word lines with a trough etched down into said well in the space defined within said buried bit lines and said second polysilicon layer, and l) an isolation area implanted into said trough.

Claim 17

A device in accordance with claim 11 wherein said isolation implant area comprises boron ions within the range of from about 5×10 12 /cm 2 to about 2×10 13 /cm 2 implanted at about 30 keV.

Claim 18

A device in accordance with claim 12 wherein said trough is about 3000Å deep.

Claim 19

A device in accordance with claim 13 wherein dielectric structures are formed on the sides of said gate and said word lines.

Claim 20

A device in accordance with claim 14 wherein a dielectric layer is formed on said trough.