Electrically conductive projections and semiconductor processing method of forming same

Claim 2

A semiconductor processing method of forming an electrically conductive projection outwardly extending from a substrate, the method comprising the following steps: providing a substrate having a projecting pillar, the substrate having an outer surface, the pillar projecting outwardly from the substrate outer surface to a first distance; providing a base layer of photoresist over the substrate outer surface to a first maximum thickness which is less than the first distance to provide the pillar projecting outwardly of the base photoresist layer; providing a base layer of electrically conductive material over the pillar and base layer of photoresist; lifting off the base photoresist layer and overlying base layer of electrically conductive material thereby providing the pillar with an electrically isolated cap of base layer electrically conductive material, the cap having top and side portions; providing an interconnecting layer of electrically conductive material over the substrate and pillar cap to a second maximum thickness, the interconnecting electrically conductive material being selectively etchable relative to the base electrically conductive material; providing a masking layer of photoresist over the interconnecting layer to a third maximum thickness, the second thickness and third thickness having a sum which is greater than the first thickness; patterning the photoresist masking layer for formation of an interconnecting material conductive line extending from the pillar cap; and after patterning, etching exposed interconnecting material from the cap and substrate to define a conductive line electrically engaging the side portion of the conductive cap.

Claim 3

The semiconductor processing method of claim 1 wherein the third thickness is less than the first distance.

Claim 4

The semiconductor processing method of claim 1 wherein the steps of patterning and etching provide the conductive line to engage the conductive cap on its side portion and not on its top portion.

Claim 5

The semiconductor processing method of claim 1 wherein the third thickness is less than the first distance, and the steps of patterning and etching provide the conductive line to engage the conductive cap on its side portion and not on its top portion.

Claim 6

The semiconductor processing method of claim 1 wherein the pillar is formed of the same material as the substrate.

Claim 7

The semiconductor processing method of claim 1 wherein the base electrically conductive material is metal.

Claim 8

The semiconductor processing method of claim 1 wherein the interconnecting electrically conductive material is metal.

Claim 9

The semiconductor processing method of claim 1 wherein the base electrically conductive material is metal, and the interconnecting electrically conductive material is metal.

Claim 10

The semiconductor processing method of claim 1 wherein the substrate and pillar comprise silicon and the base electrically conductive material is metal, the method further comprising annealing the substrate to form a metal silicide at an interface of the cap and pillar.

Claim 11

The semiconductor processing method of claim 1 wherein, the pillar is formed of the same material as the substrate; the third thickness is less than the first distance; the steps of patterning and etching provide the conductive line to engage the conductive cap on its side portion and not on its top portion; and the base electrically conductive material is metal, and the interconnecting electrically conductive material is metal.

Claim 12

The semiconductor processing method of claim 1 wherein the photoresist of the base layer and the photoresist of the masking layer comprise different photoresists, the photoresist of the masking layer having a higher viscosity than that of the base photoresist layer.

Claim 13

A semiconductor processing method of providing an electrical interconnection between adjacent different elevation areas on a substrate, the method comprising the following steps: providing a substrate having a base surface and an adjacent elevated surface, the elevated surface being spaced from the base surface by a first distance thereby defining a step having a step wall; providing a base layer of photoresist over the substrate base surface to a first maximum thickness which is less than the first distance and providing the elevated surface free of base photoresist; providing a base layer of electrically conductive material over the elevated surface, step wall and base layer of photoresist; lifting off the base photoresist layer and overlying base layer of electrically conductive material thereby providing the elevated surface with a capping layer of base electrically conductive material which is electrically isolated from the adjacent substrate base surface, the capping layer having a side portion and a top portion, the side portion extending downwardly along the step wall from the top portion and elevated surface toward but not to the substrate base surface; providing an interconnecting layer of electrically conductive material over the substrate and capping layer to a second maximum thickness, the interconnecting electrically conductive material being selectively etchable relative to the base electrically conductive material; providing a masking layer of photoresist over the interconnecting layer to a third maximum thickness, the second thickness and third thickness having a sum which is greater than the first thickness; patterning the photoresist masking layer for formation of an interconnecting material conductive line extending from the capping layer; and after patterning, etching exposed interconnecting material from the capping layer and substrate to define a conductive line electrically engaging the side portion of the capping layer.

Claim 14

A semiconductor processing method of providing an electrical interconnection between adjacent different elevation areas on a substrate, the method comprising the following steps: providing a substrate having a base surface and an adjacent elevated surface, the elevated surface being spaced from the base surface by a first distance thereby defining a step having a step wall; providing a base layer of photoresist over the substrate base surface to a first maximum thickness which is less than the first distance and providing the elevated surface free of base photoresist; providing a base layer of electrically conductive material over the elevated surface, step wall and base layer of photoresist; lifting off the base photoresist layer and overlying base layer of electrically conductive material thereby providing the elevated surface with a capping layer of base electrically conductive material which is electrically isolated from the adjacent substrate base surface, the capping layer having a side portion and a top portion, the side portion extending downwardly along the step wall from the top portion and elevated surface toward but not to the substrate base surface; providing an interconnecting layer of electrically conductive material over the substrate and capping layer to a second maximum thickness, the interconnecting electrically conductive material being selectively etchable relative to the base electrically conductive material; providing a masking layer of photoresist over the interconnecting layer to a third maximum thickness, the second thickness and third thickness having a sum which is greater than the first thickness; patterning the photoresist masking layer for formation of an interconnecting material conductive line extending from the capping layer; and after patterning, etching exposed interconnecting material from the capping layer and substrate to define a conductive line electrically engaging the side portion of the capping layer.

Claim 15

The semiconductor processing method of claim 12 wherein the third thickness is less than the first distance.

Claim 16

The semiconductor processing method of claim 12 wherein the steps of patterning and etching provide the conductive line to engage the conductive capping layer on its side portion and not on its top portion.

Claim 17

The semiconductor processing method of claim 12 wherein the third thickness is less than the first distance, and the steps of patterning and etching provide the conductive line to engage the conductive capping layer on its side portion and not on its top portion.

Claim 18

The semiconductor processing method of claim 12 wherein the base electrically conductive material is metal.

Claim 19

The semiconductor processing method of claim 12 wherein the interconnecting electrically conductive material is metal.

Claim 20

The semiconductor processing method of claim 12 wherein the base electrically conductive material is metal, and the interconnecting electrically conductive material is metal.

Claim 21

The semiconductor processing method of claim 12 wherein, the third thickness is less than the first distance; the steps of patterning and etching provide the conductive line to engage the conductive capping layer on its side portion and not on its top portion; and the base electrically conductive material is metal, and the interconnecting electrically conductive material is metal.

Claim 22

The semiconductor processing method of claim 12 wherein the photoresist of the base layer and the photoresist of the masking layer comprise different photoresists, the photoresist of the masking layer having a higher viscosity than that of the base photoresist layer.