US5477222A
Expired / Lapsed
US
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Device for encoding/decoding N-bit source words into corresponding M-bit channel words, and vice versa
Assignee: US Philips Corp
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Filing: 1994-04-06
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Granted: 1995-12-19
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Expires: 2014-04-06
Abstract
Abstract A device for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device includes a converting circuit (CM) adapted to convert the source words into corresponding m-bit channel words (y1, y2, y3). The converting circuit (CM) is further adapted to convert n-bit source words into corresponding m-bit words, such that the conversion for each n-bit source word is parity preserving (table I). The relations hold that m>n>/=1, p>/=1, and that p can vary. Preferably, m=n+1. Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.
Inventors
- 👤 Josephus A. H. M. Kahlman
- 👤 Kornelis A. Schouhamer Immink
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:31
CPC Classifications
H; H03; H03M; H03M5/00; H03M5/02; H03M5/04; H03M5/14; H03M5/145
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
110 words
A device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, wherein the bitstream of the source signal is divided into n-bit source words, which device comprises converting means adapted to convert said source words into corresponding m-bit channel words, characterized in that, the converting means are adapted to convert a block of p consecutive n-bit source words into a corresponding block of p consecutive m-bit channel words, such that the conversion for each block of p consecutive n-bit source words is parity preserving, where n, m and p are integers, m>n≧1, p≧1, and where p can vary.
Claim 2
Independent Claim
110 words
A device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, wherein the bitstream of the source signal is divided into n-bit source words, which device comprises converting means adapted to convert said source words into corresponding m-bit channel words, characterized in that, the converting means are adapted to convert a block of p consecutive n-bit source words into a corresponding block of p consecutive m-bit channel words, such that the conversion for each block of p consecutive n-bit source words is parity preserving, where n, m and p are integers, m>n≧1, p≧1, and where p can vary.
Claim 3
Dependent Claim
11 words
A device as claimed in claim 1, characterized in that, m=n+1.
Claim 4
Dependent Claim
11 words
A device as claimed in claim 2, characterized in that, n=2.
Claim 5
Dependent Claim
52 words
Device as claimed in claim 3, characterized in that, the device is adapted to convert single source words into corresponding single channel words in accordance with the following table: ______________________________________
source word channel word
______________________________________
SW.sub.1 00 CW.sub.1
101
SW.sub.2 01 CW.sub.2
100
SW.sub.3 10 CW.sub.3
001
SW.sub.4 11 CW.sub.4
000.
______________________________________
Claim 6
Dependent Claim
130 words
A device as claimed in claim 3, wherein the converting means are adapted to convert 2-bit source words into corresponding 3-bit channel words, so as to obtain a channel signal in the form of a (d,k) sequence, where d=1, the device further comprising means for detecting the position in the bitstream of the source signal where encoding of single 2-bit source words into corresponding single channel words would lead to a violation of the d-constraint at the channel word boundaries and for supplying a control signal in response to said detection, characterized in that, in the absence of the control signal, the converting means are adapted to convert single 2-bit source words into corresponding single 3-bit channel words, such that the conversion for each 2-bit source word is parity preserving.
Claim 7
Dependent Claim
146 words
Device as claimed in claim 5, wherein, in the presence of the control signal, occurring during the conversion of two consecutive source words, the converting means are adapted to convert a block of said two consecutive 2-bit source words into a block of two corresponding 3-bit channel words, such that one of the two source words in the block of source words is converted into a 3-bit channel word which is not identical to one of the four channel words CW 1 to CW 4 , in order to preserve the d=1 constraint, characterized in that, in the presence of said control signal, the converting means are further adapted to convert the block of said two subsequent 2-bit source words into a corresponding block of two subsequent 3-bit channel words, such that the conversion for said block of two subsequent 2-bit source words is parity preserving.
Claim 8
Dependent Claim
72 words
Device as claimed in claim 6, characterized in that, the converting means are adapted to convert the blocks of two consecutive 2-bit source words into the blocks of two consecutive 3-bit channel words in accordance with the coding given in the following table: ______________________________________
block of 2 source words
block of 2 channel words
______________________________________
00 00 100 010
00 01 101 010
10 00 000 010
10 01 001 010.
______________________________________
Claim 9
Dependent Claim
168 words
Device as claimed in claim 6, where k has a value larger than 5, the device being further provided with means for detecting the position in the bitstream of the source signal where encoding of single 2-bit source words into single 3-bit channel words would lead to a violation of the k-constraint and for supplying a second control signal in response to said detection, characterized in that, in the presence of the second control signal, occurring during the conversion of three consecutive 2-bit source words, the converting means are adapted to convert a block of said three consecutive 2-bit source words into a block of corresponding three consecutive 3-bit channel words, such that the conversion for said block of three 2-bit source words is parity preserving, the converting means are further adapted to convert two of the three source words in the block into corresponding 3-bit channel words not identical to the four channel words CW 1 to CW 4 , in order to preserve the k constraint.
Claim 10
Dependent Claim
78 words
Device as claimed in claim 8, characterized in that, the converting means are adapted to convert blocks of three consecutive 2-bit source words into blocks of three consecutive 3-bit channel words in accordance with the coding given in the following table: ______________________________________
block of 3 source words
block of 3 channel words
______________________________________
11 11 11 000 010 010
11 11 10 001 010 010
01 11 10 101 010 010
01 11 11 100 010 010.
______________________________________
Claim 11
Dependent Claim
38 words
Device for decoding a stream of data bits of a binary channel signal obtained by means of the encoding device in accordance with claim 1, so as to obtain a stream of databits of a binary source signal.
Claim 12
Dependent Claim
110 words
Device for decoding a stream of data bits of a binary channel signal into a stream of databits of a binary source signal, wherein the bitstream of the channel signal is divided into m-bit channel words, which device comprises deconverting means adapted to deconvert m-bit channel words into corresponding n-bit source words, characterized in that, the deconverting means are adapted to deconvert a block of p consecutive m-bit channel words into a corresponding block of p consecutive n-bit source words, such that the conversion for each block of p consecutive m-bit channel words is parity preserving, where n, m and p are integers, m>n, p≧1, and where p can vary.
Claim 13
Dependent Claim
110 words
Device for decoding a stream of data bits of a binary channel signal into a stream of databits of a binary source signal, wherein the bitstream of the channel signal is divided into m-bit channel words, which device comprises deconverting means adapted to deconvert m-bit channel words into corresponding n-bit source words, characterized in that, the deconverting means are adapted to deconvert a block of p consecutive m-bit channel words into a corresponding block of p consecutive n-bit source words, such that the conversion for each block of p consecutive m-bit channel words is parity preserving, where n, m and p are integers, m>n, p≧1, and where p can vary.
References Cited (Backward Citations)
US4337458A
Cited
US4547890A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-18 | 1999-06-19 | 1999-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-18 | 2003-06-19 | 2003-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-18 | 2007-06-19 | 2007-12-19 | $7700.00 | Window Closed / Lapsed |