Communications controller central processing unit board

Claim 1

A microprocessor based data communications controller board, including at least one microprocessor, for controlling communications between entities over a plurality of busses having different electrical specifications and using different communications procedures, the busses including a first communications bus providing a master-slave synchronous data link controlled communications system for master and slave entities, at least one second communications bus providing a Manchester encoded master-slave high-level data link controlled communications system for master and slave entities, and a third communications bus providing a processor-to-processor message passing communications system for processor entities, the controller board comprising: first interface means, coupled to said at least one microprocessor by address, data and control lines, for interfacing the microprocessor with said first communications bus providing a master-slave synchronous data link controlled communications system; second interface means, coupled to said at least one microprocessor by address, data and control lines, for interfacing the microprocessor with said at least one second communications bus providing a Manchester encoded master-slave high-level data link controlled communications system; and third interface means, coupled to said at least one microprocessor by address, data and control lines, for interfacing the microprocessor with said third communications bus providing a processor-to-processor message passing communications system; wherein said microprocessor controls the operation of said first interface means, said second interface means, and said third interface means to control the operation of said first bus, said at least one second bus, and said third bus, so that data, including control messages, are conveyed over said first bus, said at least one second bus, and said third bus, between and among said microprocessor and the respective entities; and wherein the second interface means includes: at least one serial interface controller, operatively connected to the microprocessor, for providing high-speed serial data transfer; at least one Manchester encoded data transceiver, operatively connected to the at least one serial interface controller and to the at least one second communications bus, for sending and receiving high-speed serial data between said at least one serial interface controller and said at least one second communications bus, and for encoding/decoding data on said at least one second communications bus into/from Manchester encoded data; a direct memory access controller, operatively connected to the at least one serial interface controller and to the at least one microprocessor, for providing high-speed data transfer with the at least one serial controller; an interrupt controller, operatively connected to the direct memory access controller, to the at least one serial interface controller and to the at least one microprocessor, for interrupting the microprocessor to signal that input/output is requested by said at least one serial interface controller; and a serial bus programmed logic device controller means, operatively connected to the at least one serial interface controller, to the direct memory access controller and to the at least one microprocessor, for receiving control signals from said microprocessor and for controlling operation of the second communications bus providing a Manchester encoded master-slave high-level data link controlled communications system by controlling operation of the at least one serial interface controller and the direct memory access controller.