Phase synchronization circuit having a short pull-in time and a low jitter

Claim 2

A phase synchronization circuit which includes a digital phase comparator receiving a predetermined input signal at a first input, a synchronism discrimination circuit receiving an output of said phase comparator, for discriminating a phase synchronization condition so as to output a control signal, a charge pump circuit receiving the output of said phase comparator, and controlled by said control signal, for outputting a phase differential signal, a loop filter receiving said phase differential signal of said charge pump circuit, for limiting a frequency band of said phase differential signal, a voltage controlled oscillator frequency-controlled by an output voltage of said loop filter for providing an output signal at an output terminal; and a frequency-division-circuit receiving said output signal of said voltage controlled oscillator, for frequency-dividing said output signal of said voltage controlled oscillator and for feeding back a frequency-divided output signal to a second input of said phase comparator, characterized in that said charge pump comprises: a level comparator receiving said output voltage of said loop filter for comparing it with a predetermined reference voltage so as to output a predetermined level discrimination signal, a first AND circuit receiving a first output signal of said phase comparator and said level discrimination signal, for outputting a logical product signal, an inverter receiving a second output signal of said phase comparator for outputting an inverted signal of said second output signal, a second AND circuit receiving said inverted signal outputted from said inverter and said level discrimination signal, for outputting a logical product signal, a PMOS transistor having its source connected to a voltage supply through a first constant current source, its gate connected to receive an output signal of said first AND circuit, and its drain connected to an input of said loop filter, and an NMOS transistor having its drain connected to said input of said loop filter, its gate connected to receive an output signal of said second AND circuit, and its source connected to ground through a second constant current source, a current value of said first constant current source being controlled by said control signal outputted from said synchronism discrimination circuit and said level discrimination signal, and a current value of said second constant current source being controlled by said control signal outputted from said synchronism discrimination circuit.

Claim 3

A phase synchronization circuit which includes a digital phase comparator receiving a predetermined input signal at a first input, a synchronism discrimination circuit receiving an output of said phase-comparator, for discriminating a phase synchronization condition so as to output a control signal, a charge pump circuit receiving the output of said phase comparator, and controlled by said control signal, for outputting a phase differential signal, a loop filter receiving said phase differential signal of said charge pump circuit, for limiting a frequency band of said phase differential signal, a voltage controlled oscillator frequency-controlled by an output voltage of said loop filter for providing an output signal at an output terminal, and a frequency-division circuit receiving said output signal of said voltage controlled oscillator, for frequency-dividing said output signal of said voltage controlled oscillator and for feeding back a frequency-divided output signal to a second input of said phase comparator, characterized in that said charge pump comprises: a first level comparator receiving said output voltage of said loop filter for comparing it with a first predetermined reference voltage so as to output a first predetermined level discrimination signal, a second level comparator receiving said output voltage of said loop filter for comparing it with a second predetermined reference voltage so as to output a second predetermined level discrimination signal, an AND circuit receiving a first output signal of said phase comparator and said first level discrimination signal, for outputting a logical product signal, a first OR circuit receiving an output signal of said AND circuit and said second level discrimination signal, for outputting a logical sum signal, an inverter receiving a second output signal of said phase comparator for outputting an inverted signal of said second output signal, a second OR circuit receiving an output signal of said inverter and said second level discrimination signal, for outputting a logical sum signal, a PMOS transistor having its source connected to a voltage supply through a first constant current source, its gate connected to receive an output signal of said first OR circuit, and its drain connected to an input of said loop filter, and an NMOS transistor having its drain connected to said input of said loop filter, its gate connected to receive an output signal of said second OR circuit, and its source connected to ground through a second constant current source, a current value of said first constant current source being controlled by said control signal outputted from said synchronism discrimination circuit and said first level discrimination signal, and, a current value of said second constant current source being controlled by said control signal outputted from said synchronism discrimination circuit and said second level discrimination signal.

Claim 4

A phase synchronization circuit which includes a digital phase comparator receiving a predetermined input signal at a first input, a synchronism discrimination circuit receiving an output of said phase-comparator, for discriminating a phase synchronization condition so as to output a control signal, a charge pump circuit receiving the output of said phase comparator, and controlled by said control signal, for outputting a phase differential signal, a loop filter receiving said phase differential signal of said charge pump circuit, for limiting a frequency band of said phase differential signal, a voltage controlled oscillator frequency-controlled by an output voltage of said loop filter for providing an output signal at an output terminal, and a frequency-division circuit receiving said output signal of said voltage controlled oscillator, for frequency-dividing said output signal of said voltage controlled oscillator and for feeding back a frequency-divided output signal to a second input of said phase comparator, characterized in that said charge pump comprises: a first level comparator receiving said output voltage of said loop filter for comparing it with a first predetermined reference voltage so as to output a first predetermined level discrimination signal, a second level comparator receiving said output voltage of said loop filter for comparing it with a second predetermined reference voltage so as to output a second predetermined level discrimination signal, an AND circuit receiving a first output signal of said phase comparator and said first level discrimination signal, for outputting a logical product signal, a first OR circuit receiving an output signal of said AND circuit and said second level discrimination signal, for outputting a logical sum signal, an inverter receiving a second output signal of said phase comparator for outputting an inverted signal of said second output signal, a second OR circuit receiving an output signal of said inverter and said second level discrimination signal, for outputting a logical sum signal, a PMOS transistor having its source connected to a voltage supply through a first constant current source, its gate connected to receive an output signal of said first OR circuit, and its drain connected to an input of said loop filter, and an NMOS transistor having its drain connected to said input of said loop filter, its gate connected to receive an output signal of said second OR circuit, and its source connected to ground through a second constant current source, a current value of said first constant current source being controlled by said control signal outputted from said synchronism discrimination circuit and said first level discrimination signal, and, a current value of said second constant current source being controlled by said control signal outputted from said synchronism discrimination circuit and said second level discrimination signal.

Claim 5

A phase synchronization circuit claimed in claim 2 wherein said charge pump further comprises a second AND circuit receiving said output signal of said inverter and said first level discrimination signal, for outputting a logical product signal, which is supplied to said second OR circuit as said output signal of said inverter.