US5473618A
Expired / Lapsed
US
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Semiconductor integrated circuit having a built-in test circuit
Assignee: NEC Corp
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Filing: 1993-12-27
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Granted: 1995-12-05
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Expires: 2013-12-27
Abstract
Abstract The semiconductor integrated circuit having a built-in test circuit of the present invention is an IC having a circuit for screening products for shipment by measuring the maximum operating frequency of the IC by outputting the propagation state of a signal within the test circuit within an operation cycle of the IC, the circuit being composed of: an external clock pulse input terminal; a clock driver that inputs the external clock pulse and converts it to clock pulses of two phases, one being in phase with the external clock pulse and the other being in reverse phase; a test terminal into which is inputted a test execution signal; a one-shot circuit that generates a high-active output pulse when an active signal is inputted; a sequential circuit that performs transition of an output value in accordance with an output pulse from the one-shot circuit; a test circuit made up of a number n of latch circuits of identical or differing structure that hold and successively output to a next circuit a high-level signal D of an inputted logic value 1; a test register made up of a number n of serially connected latch circuits that hold the output of each of the latch circuits of the test circuit; and a data selector that switches between outputting to a number n of output terminals either the output value of the test circuit or the operation output of the IC.
Inventors
- 👤 Yuuichi Takeshita
- 👤 Masashi Arai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:02
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/30
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
129 words
An semiconductor integrated circuit having a built-in test circuit wherein the test circuit has a plurality of serially connected latch circuits of a predictable switching speed, characterized in that: the held values in all of the latch circuits of the test circuit are reset to a logic value 0 according to a clock pulse inputted from the outside; a signal of logic value 1 is inputted to the first latch circuit of the test circuit; the signal of logic value 1 inputted to the first latch circuit is both sequentially propagated to and held by each of the latch circuits; and for every cycle designated by the clock pulse inputted from the outside, the held values of each of the latch circuits are simultaneously outputted to external output terminals.
Claim 2
Dependent Claim
129 words
An semiconductor integrated circuit having a built-in test circuit wherein the test circuit has a plurality of serially connected latch circuits of a predictable switching speed, characterized in that: the held values in all of the latch circuits of the test circuit are reset to a logic value 0 according to a clock pulse inputted from the outside; a signal of logic value 1 is inputted to the first latch circuit of the test circuit; the signal of logic value 1 inputted to the first latch circuit is both sequentially propagated to and held by each of the latch circuits; and for every cycle designated by the clock pulse inputted from the outside, the held values of each of the latch circuits are simultaneously outputted to external output terminals.
Claim 3
Dependent Claim
242 words
A semiconductor integrated circuit having a built-in test circuit and comprising: a clock driver that converts a single-phase clock pulse inputted from the outside to clock pulses of two phases, one in phase with the inputted clock pulse and the other in reverse phase; a test terminal to which is inputted an active signal that directs a test execution; a one-shot circuit that generates a high-active output pulse when an active signal is inputted to the test terminal; a sequential circuit that is reset in accordance with an output pulse from the one-shot circuit and that outputs a plurality of state value signals on which transitions have been performed according to the output clock pulse of the clock driver; a test circuit that is reset in accordance with an output pulse from the one-shot circuit and in which a plurality of levels of latch circuits are serially connected that, in accordance with output of the sequential circuit, successively transmit and hold inputted logic value 1; a test register that is reset in accordance with an output pulse from the one-shot circuit, and that, in accordance with the output of the sequential circuit, holds the output value of each of the latch circuits making up the test circuit; and a data selector that, in accordance with output from the sequential circuit, switches between outputting to an output terminal either the held value of the test register or the operation output of the IC.
Claim 4
Dependent Claim
242 words
A semiconductor integrated circuit having a built-in test circuit and comprising: a clock driver that converts a single-phase clock pulse inputted from the outside to clock pulses of two phases, one in phase with the inputted clock pulse and the other in reverse phase; a test terminal to which is inputted an active signal that directs a test execution; a one-shot circuit that generates a high-active output pulse when an active signal is inputted to the test terminal; a sequential circuit that is reset in accordance with an output pulse from the one-shot circuit and that outputs a plurality of state value signals on which transitions have been performed according to the output clock pulse of the clock driver; a test circuit that is reset in accordance with an output pulse from the one-shot circuit and in which a plurality of levels of latch circuits are serially connected that, in accordance with output of the sequential circuit, successively transmit and hold inputted logic value 1; a test register that is reset in accordance with an output pulse from the one-shot circuit, and that, in accordance with the output of the sequential circuit, holds the output value of each of the latch circuits making up the test circuit; and a data selector that, in accordance with output from the sequential circuit, switches between outputting to an output terminal either the held value of the test register or the operation output of the IC.
Claim 5
Dependent Claim
33 words
The semiconductor integrated circuit having a built-in test circuit according to claim 2 wherein the internal circuits of all of the latch circuits making up the test circuit are of the same construction.
Claim 6
Dependent Claim
37 words
The semiconductor integrated circuit having a built-in test circuit according to claim 2 wherein at least one internal circuit of the internal circuits of the latch circuits making up the test circuit is of different circuit structure.
References Cited (Backward Citations)
US5109383A
Cited
US5210759A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |