US5471601A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory device and method for avoiding live lock of a DRAM with cache
Assignee: Intel Corp
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Filing: 1992-06-17
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Granted: 1995-11-28
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Expires: 2012-06-17
Abstract
Abstract A method and apparatus for allowing two or more masters, such as central processing units (CPUs), to read a dynamic random access memory (DRAM) device which includes a cache connected to a main memory block. When a CPU provides a read request, the DRAM has a first logic circuit that compares addresses requested with addresses stored in the cache. If the addresses are the same, the DRAM sends an acknowledge (ACK) signal to that CPU and sends the data to the processor. If the addresses are not the same, the DRAM sends a no acknowledge (NACK) signal to the CPU and transfers the requested data from the main memory block to the cache. The DRAM has a second logic circuit that contains a latch which is set when the DRAM sends a NACK signal and reset when the DRAM sends a subsequent ACK signal. The second logic circuit is connected to the first logic circuit to disable the first logic circuit and prevent a cache fetch from main memory when the latch has been set. The second logic circuit is also connected to a refresh controller of the DRAM to prevent a refresh cycle when the latch is set. Both the first logic circuit and the refresh controller are enabled when the latch is reset.
Inventors
- 👤 Mark A. Gonzales
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:23
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/084; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/1652; G06F13/1663
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
212 words
A memory device that is coupled to a master device which provides a first request package that has a first request address, comprising: a main memory block; a cache that is connected to said main memory block and has a cache address; a first logic circuit that is connected to said cache and said main memory block and which compares said first request address with said cache address, and performs a first cache fetch such that data associated with said first request address is transferred from said main memory block to said cache when said cache does not contain the first request address, wherein said first logic circuit provides an acknowledge (ACK) signal when said cache contains said first request address and provides a no acknowledge (NACK) signal when said cache does not contain said first request address; and, a latching logic circuit connected to said main memory block and said first logic circuit, said latching logic circuit being set and preventing a second cache fetch when said cache does not contain the first request address and the NACK signal is provided, and is reset and allows the second cache fetch when said cache contains the first request address and the ACK signal is provided when the first request package is resubmitted.
Claim 2
Dependent Claim
212 words
A memory device that is coupled to a master device which provides a first request package that has a first request address, comprising: a main memory block; a cache that is connected to said main memory block and has a cache address; a first logic circuit that is connected to said cache and said main memory block and which compares said first request address with said cache address, and performs a first cache fetch such that data associated with said first request address is transferred from said main memory block to said cache when said cache does not contain the first request address, wherein said first logic circuit provides an acknowledge (ACK) signal when said cache contains said first request address and provides a no acknowledge (NACK) signal when said cache does not contain said first request address; and, a latching logic circuit connected to said main memory block and said first logic circuit, said latching logic circuit being set and preventing a second cache fetch when said cache does not contain the first request address and the NACK signal is provided, and is reset and allows the second cache fetch when said cache contains the first request address and the ACK signal is provided when the first request package is resubmitted.
Claim 3
Dependent Claim
47 words
The memory device as recited in claim 1, further comprising a refresh controller that refreshes said main memory block, said refresh controller being connected to said latching logic circuit such that said refresh controller is disabled until the first request package is resubmitted by the master device.
Claim 4
Dependent Claim
271 words
A computer system, comprising: a main memory block; a refresh controller that performs a refresh operation on said main memory block; a cache that is connected to said main memory block and has a cache address; a data bus connected to said cache; a first master device connected to said data bus for generating a first request package that contains a first request address; a second master device connected to said data bus for generating a second request package that contains a second request address; a first logic circuit that is connected to said cache, said main memory block and said data bus and which compares said first request address with said cache address, and performs a first cache fetch such that data associated with said first request address is transferred from said main memory block to said cache when said cache does not contain the first request address, wherein said first logic circuit provides an acknowledge (ACK) signal when said cache contains said first request address and provides a no acknowledge (NACK) signal when said cache does not contain said first request address; and, a latching logic circuit connected to said main memory block, said first logic circuit and said refresh controller, said latching logic circuit being set and preventing both the refresh operation and a second cache fetch when said cache does not contain the first request address and the NACK signal is provided, and is reset and allows both the refresh operation and the second cache fetch when said cache contains the first request address and the ACK signal is provided when the first request package is resubmitted.
Claim 5
Dependent Claim
271 words
A computer system, comprising: a main memory block; a refresh controller that performs a refresh operation on said main memory block; a cache that is connected to said main memory block and has a cache address; a data bus connected to said cache; a first master device connected to said data bus for generating a first request package that contains a first request address; a second master device connected to said data bus for generating a second request package that contains a second request address; a first logic circuit that is connected to said cache, said main memory block and said data bus and which compares said first request address with said cache address, and performs a first cache fetch such that data associated with said first request address is transferred from said main memory block to said cache when said cache does not contain the first request address, wherein said first logic circuit provides an acknowledge (ACK) signal when said cache contains said first request address and provides a no acknowledge (NACK) signal when said cache does not contain said first request address; and, a latching logic circuit connected to said main memory block, said first logic circuit and said refresh controller, said latching logic circuit being set and preventing both the refresh operation and a second cache fetch when said cache does not contain the first request address and the NACK signal is provided, and is reset and allows both the refresh operation and the second cache fetch when said cache contains the first request address and the ACK signal is provided when the first request package is resubmitted.
Claim 6
Dependent Claim
21 words
The system as recited in claim 3, wherein said first and second master devices are each a central processing unit (CPU).
Claim 7
Dependent Claim
52 words
The system as recited in claim 4, wherein said first request package includes a coded signal which is indicative of one of said first and second master devices, said latching logic circuit stores said coded signal and disables said main memory block and said refresh controller until said coded signal is resubmitted.
Claim 8
Dependent Claim
16 words
The system as recited in claim 5, wherein said coded signal is said first request address.
Claim 9
Dependent Claim
33 words
The system as recited in claim 5, wherein the coded signal for said first master device is a binary 0 and the coded signal for said second master device is a binary 1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-27 | 1999-05-29 | 1999-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-27 | 2003-05-29 | 2003-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-27 | 2007-05-29 | 2007-11-28 | $7700.00 | Window Closed / Lapsed |