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US5470800A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for forming an interlayer film

Assignee: Sony Corp
•
Filing: 1993-03-26
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Granted: 1995-11-28
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Expires: 2013-03-26
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Abstract

Abstract A process for forming an interlayer membrane by chemical vapor deposition comprises the steps of supplying gaseous materials to a reaction chamber in which a wafer to be deposited is installed, supplying a catalyst gas to the reaction chamber separately from but concurrently with the gaseous materials are supplied, and allowing the gaseous materials to react with the catalyst gas adjacent the surface of the wafer to form a membrane being laid on the wafer. The gaseous materials may include at least one organic silicone compound. The catalyst may be selected from water soluble catalysts having basicity, preferably, compounds having amino groups or hydrazine derivatives. The catalyst may be dissolved with water to a solution prior to supply. An apparatus for forming such interlayer membrane by chemical vapor deposition is composed of a reaction chamber in which a semiconductor substrate to be deposited, means for supplying gaseous materials communicated with the reaction chamber to supply the gaseous materials to adjacent the substrate in the reaction chamber, and means for supplying a catalyst communicated with the reaction chamber separately from the means for supplying gaseous materials to separately supply the catalyst to adjacent the substrate in the reaction chamber.

Inventors

  • 👤 Masakazu Muroyama

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 18:15
CPC Classifications
C; C23; C23C; C23C16/00; C23C16/44; C23C16/455; C23C16/45514; C23C16/22; C23C16/30; C23C16/40; C23C16/401; C23C16/402; H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/6338; H10P14/66; H10P14/662; H10W; H10W20/00; H10W20/01; H10W20/071; H10P14/668; H10P14/6681; H10P14/6684; H10P14/6686; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6922; Y; Y10; Y10S; Y10S438/00; Y10S438/903

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 288 words
A process for forming a semiconductor device comprising: providing a wafer including a semiconductor substrate having an oxidized silicone insulating layer thereon having aluminum wirings including clearances defined thereon; forming a first insulating interlayer on said aluminum wirings and insulating layer by a chemical vapor deposition process wherein a gaseous material including at least one organic silicone compound and free from water is introduced into a reaction chamber containing said wafer until membrane formation is started and thereafter introducing a dehydration condensation catalyst into said reaction chamber to provide a high molecular weight first insulating interlayer on said wafer having a reduced concentration of hydroxyl groups as compared to a similar interlayer formed by hydrolysis; forming a second insulating interlayer on said first insulating interlayer by a chemical vapor deposition process wherein a gaseous material including at least one organic silicone compound, an oxidant and a dehydration condensation catalyst are introduced into the reaction chamber and reacted until a second insulating interlayer is formed on the wafer; etching said second insulation interlayer back so that said second insulating interlayer remains only in the clearances of the wirings; and thereafter forming a third insulating interlayer on said wafer by a chemical vapor deposition process wherein a gaseous material including at least one organic silicone compound and free from water is introduced into a reaction chamber containing said wafer until membrane formation is started and thereafter introducing a dehydration condensation catalyst into said reaction chamber to provide a high molecular weight third insulating interlayer on said wafer having a reduced concentration of hydroxyl groups as compared to a similar interlayer formed by hydrolysis; whereby said wafer may be annealed with less shrinkage and cracking to provide an improved semiconductor device.
Claim 2
Dependent Claim 288 words
A process for forming a semiconductor device comprising: providing a wafer including a semiconductor substrate having an oxidized silicone insulating layer thereon having aluminum wirings including clearances defined thereon; forming a first insulating interlayer on said aluminum wirings and insulating layer by a chemical vapor deposition process wherein a gaseous material including at least one organic silicone compound and free from water is introduced into a reaction chamber containing said wafer until membrane formation is started and thereafter introducing a dehydration condensation catalyst into said reaction chamber to provide a high molecular weight first insulating interlayer on said wafer having a reduced concentration of hydroxyl groups as compared to a similar interlayer formed by hydrolysis; forming a second insulating interlayer on said first insulating interlayer by a chemical vapor deposition process wherein a gaseous material including at least one organic silicone compound, an oxidant and a dehydration condensation catalyst are introduced into the reaction chamber and reacted until a second insulating interlayer is formed on the wafer; etching said second insulation interlayer back so that said second insulating interlayer remains only in the clearances of the wirings; and thereafter forming a third insulating interlayer on said wafer by a chemical vapor deposition process wherein a gaseous material including at least one organic silicone compound and free from water is introduced into a reaction chamber containing said wafer until membrane formation is started and thereafter introducing a dehydration condensation catalyst into said reaction chamber to provide a high molecular weight third insulating interlayer on said wafer having a reduced concentration of hydroxyl groups as compared to a similar interlayer formed by hydrolysis; whereby said wafer may be annealed with less shrinkage and cracking to provide an improved semiconductor device.
Claim 3
Dependent Claim 29 words
A process as defined in claim 1, wherein said at least one organic silicone compound is selected from the group consisting of alkoxysilanes, alkoxyacetoxysilanes, chain polysiloxanes and cyclic polysiloxanes.
Claim 4
Dependent Claim 26 words
A process as defined in claim 1, wherein the dehydration condensation catalyst is selected from the group consisting of ammonia, alkylamines and water soluble hydrazine derivatives.
Claim 5
Dependent Claim 12 words
A process as defined in claim 1, wherein said oxidant is water.
Claim 6
Dependent Claim 24 words
A process as defined in claim 1, wherein said chemical vapor deposition processes are performed at temperatures of from 100° C. to 200° C.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-11-27 1999-05-29 1999-11-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-11-27 2003-05-29 2003-11-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-11-27 2007-05-29 2007-11-28 $7700.00 Window Closed / Lapsed

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