Deflection apparatus for raster scanned CRT displays

Claim 2

Deflection apparatus for a raster scanned cathode ray tube display, the apparatus comprising: a flyback circuit (T2,T4,Ly,Df,Cf) including a switch (T2,T4) comprising a bipolar transistor (T4) connected in series with an inductor (Ly), the switch (T2,T4) being responsive to a line drive signal (LINE) to alternately open and close a current path through the inductor (Ly) between a first voltage level (B+) and a second voltage level (0 V) lower than the first voltage level (B+) to generate a raster scan current signal in a deflection coil of the display, the amplitude of the raster scan signal being determined as a function of the first voltage level (B+) and the frequency of the line drive signal (LINE); a feedback circuit (D2,R3,D3,C2) connected to the base electrode of the bipolar transistor T4 for generating a feedback signal (F) as a function of current flowing out of the transistor (T4) via the base electrode of the bipolar transistor (T4); and a regulator (600-630,T3,L,D1,C1) connected to the flyback circuit (T2,T4,Ly,Df,Cf) for varying the first voltage level (B+) as a function of the feedback signal (F) to maintain a constant raster scan width despite variations in the frequency of the line drive signal (LINE).

Claim 3

Apparatus as claimed in claim 1, wherein the feedback circuit (D2,R3,D3,C2) comprises a sense resistor (R3) in a current path between the base electrode of the bipolar transistor (T4) and the second voltage level (0 V), the feedback signal (F) being determined by a voltage signal produced across the sense resistor (R3) as a function of current flowing from the base electrode of the transistor (T4) and through the sense resistor (R3) towards the second voltage level.

Claim 4

Apparatus as claimed in claim 2, wherein the feedback circuit (D2,R3,D3,C2) comprises a peak detector (D3,C2) connected to the sense resistor (R3), the feedback signal (F) being determined by a voltage level generated by the peak detector (D3,C2) in response to the voltage signal produced across the sense resistor (R3).

Claim 5

Apparatus as claimed in claim 1, wherein the switch (T2,T4) comprises a field effect transistor (T2) connected in series with the bipolar transistor (T4) in an emitter switching configuration, the gate electrode of the field effect transistor (T2) being connected to receive the line drive signal (LINE) to alternately open and close the current path through the inductor (Ly) between the first voltage level (B+) and the second voltage level (0 V).

Claim 6

Apparatus as claimed in claim 4, wherein the bipolar transistor (T4) is an NPN transistor, the collector electrode of the bipolar transistor (T4) being connected to the inductor (Ly), the emitter electrode of the bipolar transistor (T4) being connected to the field effect transistor (T2), current flowing from the inductor (Ly) into the collector electrode of the bipolar transistor (T4) and out of the base electrode of the bipolar transistor (T4) in response to the field effect transistor (T2) turning off.

Claim 7

Apparatus as claimed in claim 1, wherein the regulator (600-630,T3,L,D1,C1) comprises a boost circuit (T3,L,D1,C1) connected to the flyback circuit (T2,T4,Ly,Df,Cf) the boost circuit (T3,L,D1,C1) comprising a second inductor (L) connected in series with a second switch (T3), the second switch (T3) being responsive to a pulse signal (PWM) synchronised to the line drive signal (LINE) to alternately open and close a current path through the second inductor (L) between the second voltage level (0 V) and a third voltage level higher than the second voltage level (Vin) to generate the first voltage level (B+), the first voltage level (B+) being determined as a function of the third voltage level (Vin) and the width of the pulses of the pulse signal (PWM), the regulator (600-630,T3,L,D1,C1) being connected to the boost circuit (T3,L,D1,C1) for varying the width of the pulses of the pulse signal (PWM) as a function of the amplitude of the line scan signal.

Claim 8

Apparatus as claimed in claim 1, wherein the inductor (Ly) includes the raster deflection coil.

Claim 9

Apparatus as claimed in claim 1, wherein the regulator (600-630,T3,L,D1,C1) comprises an error amplifier (600) connected to the feedback circuit (D2,R3,D3,C2) for generating an error signal as a function of the difference between the feedback signal (F) and a reference level, and a pulse width modulator (R1,610,620) connected to the error amplifier (600) and the boost circuit (T3,L,D1,C1) for modulating the width of the pulse signal (PWM) as a function of the error signal.

Claim 10

Apparatus as claim 8, wherein the pulse width modulator (R1,610,620) comprises: a current sensor (R1) connected to the boost circuit (T3,L,D1,C1) for generating a ramp signal as a function of current flowing in the second current path; a comparator (610) connected to the error amplifier (600) for generating an output signal when the ramp signal exceeds the error signal; and a latch (620) connected to the boost circuit (T3,L,D1,C1) and the comparator (610) for generating the pulse signal (PWM) at the control electrode of the second transistor switch (T2), the latch being set in response to the rising edge of the line drive signal, and the latch (620) being reset in response to the output signal from the comparator (610).

Claim 11

Apparatus as claimed in claim 1, in combination with a display having a cathode ray tube, the cathode ray tube being driven by said apparatus.

Claim 12

Deflection apparatus for a raster scanned cathode ray tube display, the apparatus comprising: a ramp generator having a flyback circuit (T2, Lc, Cf; T2, Ly, Cf) including a first inductor (Lc; Ly) connected in series with a first transistor switch (T2), the first transistor switch (T2) being responsive to a line drive signal (LINE) to alternately open and close a current path through the first inductor (Lc; Ly) between a first voltage level (B+) and a second voltage level (0 V) lower than the first voltage level (B+) to generate a raster scan current signal in a deflection coil (Ly) of the display, the amplitude of the raster scan current signal being determined as a function of the first voltage level (B+) and the frequency of the line drive switching signal (LINE), and a boost circuit (T3, L, D1, C1; T3, L, D1, Cs) connected to the flyback circuit (T2, Lc, Cf; T2, Ly, Cf), the boost circuit (T3, L, D1, C1; T3, L, D1, Cs) comprising a second inductor (L) connected in series with a second transistor switch (T3), the second transistor switch (T3) being responsive to a pulse signal (PWM) synchronized to the line drive signal (LINE) to alternately open and close a current path through the second inductor (L) between the second voltage level (0 V) and a third voltage level higher than the second voltage level (Vin) to generate the first voltage level (B+), the first voltage level (B+) being determined as a function of the third voltage level (Vin) and the width of the pulses of the pulse signal (PWM); and a regulator connected (230) to the flyback circuit (T2, Lc, Cf; T2, Ly, Cf) and the boost circuit (T3, L, C1; T3, L, Cs) for varying the width of the pulses of the pulse signal (PWM) as a function of the amplitude of the line scan signal to maintain a constant raster line width as the frequency of the line drive signal is varied; wherein the regulator comprises: a feedback circuit connected to the flyback circuit for generating a feedback signal as a function of the amplitude of the voltage impulse signal; an error amplifier connected to the feedback circuit for generating an error signal as a function of the difference between the feedback signal and a reference level, and a pulse width modulator connected to the error amplifier and the boost circuit for modulating the width of the pulse signal as a function of the error signal; wherein the pulse width modulator (R1, 610, 620) comprises: a current sensor (R1) connected to the boost circuit (T3, L, D1, C1) for generating a ramp signal as a function of current flowing in the second current path; a comparator (610) connected to the error amplifier (600) for generating an output signal when the ramp signal exceeds the error signal; and a latch (620) connected to the boost circuit (T3, L, D1, C1) and the comparator (610) for generating the pulse signal (PWM) at the control electrode of the second transistor switch (T2), the latch being set in response to the rising edge of the line drive signal, and the latch (620) being reset in response to the output signal from the comparator (610).

Claim 13

Deflection apparatus for a raster scanned cathode ray tube display, the apparatus comprising: a ramp generator having a flyback circuit (T2, Lc, Cf; T2, Ly, Cf) including a first inductor (Lc; Ly) connected in series with a first transistor switch (T2), the first transistor switch (T2) being responsive to a line drive signal (LINE) to alternately open and close a current path through the first inductor (Lc; Ly) between a first voltage level (B+) and a second voltage level (0 V) lower than the first voltage level (B+) to generate a raster scan current signal in a deflection coil (Ly) of the display, the amplitude of the raster scan current signal being determined as a function of the first voltage level (B+) and the frequency of the line drive switching signal (LINE), and a boost circuit (T3, L, D1, C1; T3, L, D1, Cs) connected to the flyback circuit (T2, Lc, Cf; T2, Ly, Cf), the boost circuit (T3, L, D1, C1; T3, L, D1, Cs) comprising a second inductor (L) connected in series with a second transistor switch (T3), the second transistor switch (T3) being responsive to a pulse signal (PWM) synchronized to the line drive signal (LINE) to alternately open and close a current path through the second inductor (L) between the second voltage level (0 V) and a third voltage level higher than the second voltage level (Vin) to generate the first voltage level (B+), the first voltage level (B+) being determined as a function of the third voltage level (Vin) and the width of the pulses of the pulse signal (PWM); and a regulator connected (230) to the flyback circuit (T2, Lc, Cf; T2, Ly, Cf) and the boost circuit (T3, L, C1; T3, L, Cs) for varying the width of the pulses of the pulse signal (PWM) as a function of the amplitude of the line scan signal to maintain a constant raster line width as the frequency of the line drive signal is varied; wherein the regulator comprises: a feedback circuit connected to the flyback circuit for generating a feedback signal as a function of the amplitude of the voltage impulse signal; an error amplifier connected to the feedback circuit for generating an error signal as a function of the difference between the feedback signal and a reference level, and a pulse width modulator connected to the error amplifier and the boost circuit for modulating the width of the pulse signal as a function of the error signal; wherein the pulse width modulator (R1, 610, 620) comprises: a current sensor (R1) connected to the boost circuit (T3, L, D1, C1) for generating a ramp signal as a function of current flowing in the second current path; a comparator (610) connected to the error amplifier (600) for generating an output signal when the ramp signal exceeds the error signal; and a latch (620) connected to the boost circuit (T3, L, D1, C1) and the comparator (610) for generating the pulse signal (PWM) at the control electrode of the second transistor switch (T2), the latch being set in response to the rising edge of the line drive signal, and the latch (620) being reset in response to the output signal from the comparator (610).

Claim 14

Apparatus as claimed in claim 11, wherein the first inductor includes the raster deflection coil.

Claim 15

Apparatus as claimed in claim 11, wherein the regulator is adapted to vary the width of the pulses of the pulse signal as a function of an East-West pin cushion distortion correction signal.

Claim 16

A computer system comprising: a processor for generating raster synchronisation signals and for varying the frequency of at least one of the raster synchronisation signals to produce different display modes; and a CRT display as claimed in claim 9 connected to the processor for producing a picture on the display in response to the raster synchronisation signals and for maintaining the size of the picture substantially constant between the different display modes.

Claim 17

Apparatus as claimed in claim 11, wherein the boost circuit includes an S correction capacitor.

Claim 18

Apparatus as claimed in claim 11, in combination with a display having a cathode ray tube, the cathode ray tube being driven by said apparatus.

Claim 19

Apparatus as claimed in claim 12, wherein the regulator is adapted to vary the width of the pulses of the pulse signal as a function of an East-West pin cushion distortion correction signal.

Claim 20

Apparatus for generating an anode voltage for a CRT display, the generator comprising: a flyback circuit (T2', Tr1) including a transformer (Tr1) having a primary winding connected in series with a first transistor switch (T2'), the first transistor switch (T2') being responsive to a line drive switching signal (LINE) to alternately open and close a current path through the primary winding between a first voltage level (B+') and a second voltage level (0 V) lower than the first voltage level (B+') to generate a voltage impulse signal across the primary winding, the amplitude of the voltage impulse signal being determined as a function of the first voltage level (B+') and the frequency of the line drive switching signal (LINE), and a boost circuit (L', T1', D1', C') connected to the flyback circuit (T2', Tr1), the boost circuit (L', T1', D1', C') comprising an inductor (L') connected in series with a second transistor switch (T1'), the second transistor switch (T1') being responsive to a pulse signal (PWM') synchronised to the line drive signal (LINE) to alternately open and close a current path through the inductor (L') between the second voltage level (0 V) and a third voltage level (Vin) higher than the second voltage level (0 V) to generate the first voltage level (B+'), the first voltage level (B+') being determined as a function of the third voltage level (Vin) and the width of the pulses of the pulse signal (PWM'); and a regulator (700, 710, 720) connected to the flyback circuit (T2', Tr1) and the boost circuit (L', T1', D1', C') for varying the width of the pulses of the pulse signal (PWM') as a function of the amplitude of the voltage impulse signal to maintain a constant anode voltage as the frequency of the line drive signal is varied; wherein the regulator comprises: a feedback circuit connected to the flyback circuit for generating a feedback signal as a function of the amplitude of the voltage impulse signal; an error amplifier connected to the feedback circuit for generating an error signal as a function of the difference between the feedback signal and a reference level, and a pulse width modulator connected to the error amplifier and the boost circuit for modulating the width of the pulse signal as a function of the error signal; wherein the pulse width modulator (R1, 610, 620) comprises: a current sensor (R1) connected to the boost circuit (T3, L, D1, C1) for generating a ramp signal as a function of current flowing in the second current path; a comparator (610) connected to the error amplifier (600) for generating an output signal when the ramp signal exceeds the error signal; and a latch (620) connected to the boost circuit (T3, L, D1, C1) and the comparator (610) for generating the pulse signal (PWM) at the control electrode of the second transistor switch (T2), the latch being set in response to the rising edge of the line drive signal, and the latch (620) being reset in response to the output signal from the comparator (610).

Claim 21

Apparatus for generating an anode voltage for a CRT display, the generator comprising: a flyback circuit (T2', Tr1) including a transformer (Tr1) having a primary winding connected in series with a first transistor switch (T2'), the first transistor switch (T2') being responsive to a line drive switching signal (LINE) to alternately open and close a current path through the primary winding between a first voltage level (B+') and a second voltage level (0 V) lower than the first voltage level (B+') to generate a voltage impulse signal across the primary winding, the amplitude of the voltage impulse signal being determined as a function of the first voltage level (B+') and the frequency of the line drive switching signal (LINE), and a boost circuit (L', T1', D1', C') connected to the flyback circuit (T2', Tr1), the boost circuit (L', T1', D1', C') comprising an inductor (L') connected in series with a second transistor switch (T1'), the second transistor switch (T1') being responsive to a pulse signal (PWM') synchronised to the line drive signal (LINE) to alternately open and close a current path through the inductor (L') between the second voltage level (0 V) and a third voltage level (Vin) higher than the second voltage level (0 V) to generate the first voltage level (B+'), the first voltage level (B+') being determined as a function of the third voltage level (Vin) and the width of the pulses of the pulse signal (PWM'); and a regulator (700, 710, 720) connected to the flyback circuit (T2', Tr1) and the boost circuit (L', T1', D1', C') for varying the width of the pulses of the pulse signal (PWM') as a function of the amplitude of the voltage impulse signal to maintain a constant anode voltage as the frequency of the line drive signal is varied; wherein the regulator comprises: a feedback circuit connected to the flyback circuit for generating a feedback signal as a function of the amplitude of the voltage impulse signal; an error amplifier connected to the feedback circuit for generating an error signal as a function of the difference between the feedback signal and a reference level, and a pulse width modulator connected to the error amplifier and the boost circuit for modulating the width of the pulse signal as a function of the error signal; wherein the pulse width modulator (R1, 610, 620) comprises: a current sensor (R1) connected to the boost circuit (T3, L, D1, C1) for generating a ramp signal as a function of current flowing in the second current path; a comparator (610) connected to the error amplifier (600) for generating an output signal when the ramp signal exceeds the error signal; and a latch (620) connected to the boost circuit (T3, L, D1, C1) and the comparator (610) for generating the pulse signal (PWM) at the control electrode of the second transistor switch (T2), the latch being set in response to the rising edge of the line drive signal, and the latch (620) being reset in response to the output signal from the comparator (610).

Claim 22

Apparatus as claimed in claim 18, wherein the boost circuit includes an S correction capacitor.

Claim 23

Apparatus as claimed in claim 18, in combination with a display having a cathode ray tube, the cathode ray tube being driven by said apparatus.