US5468677A
Expired / Lapsed
US
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Isolation structure of semiconductor device and method for forming the same
Assignee: SK Hynix Inc
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Filing: 1994-12-21
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Granted: 1995-11-21
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Expires: 2014-12-21
Abstract
Abstract An isolation structure of a semiconductor device including a channel stop diffusion region selectively formed on a portion of a single crystalline silicon substrate disposed beneath an edge of a field oxide film formed on the substrate, thereby capable of selectively increasing, irrespective of a pattern size of the field region, a channel ion concentration at an edge of a field region where the field region is connected to an active region and which region is a weak area serving to decrease a channel stop ion concentration at an interface between the field oxide film and the silicon substrate and to decrease a threshold voltage of a field transistor due to a small thickness thereof and thereby locally increasing the threshold voltage. By the local increase in threshold voltage, it is possible to prevent a degradation in insulating characteristic of the field transistor with a small pattern size.
Inventors
- 👤 Young K. Jun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:12
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
95 words
A method for forming an isolation structure of a semiconductor device, comprising the steps of: forming an insulating film on a first portion of a substrate except for a field region; forming a field insulating film on a second portion of the substrate corresponding to the field region; partially exposing the second surface portion of the substrate by a predetermined width along an edge of the field insulating film; implanting channel stop ions in the exposed portion of the substrate; and annealing the implanted channel stop ions and thereby forming a channel stop diffusion region.
Claim 2
Independent Claim
95 words
A method for forming an isolation structure of a semiconductor device, comprising the steps of: forming an insulating film on a first portion of a substrate except for a field region; forming a field insulating film on a second portion of the substrate corresponding to the field region; partially exposing the second surface portion of the substrate by a predetermined width along an edge of the field insulating film; implanting channel stop ions in the exposed portion of the substrate; and annealing the implanted channel stop ions and thereby forming a channel stop diffusion region.
Claim 3
Dependent Claim
39 words
The method in accordance with claim 1, wherein the step of partially exposing the second surface portion of the substrate comprises the step of etching the edge of the field insulating film using the insulating film as a mask.
Claim 4
Dependent Claim
35 words
The method in accordance with claim 1, wherein the step of implanting channel stop ions is carried out under a condition that the insulating film and the field insulating film are used as a mask.
Claim 5
Independent Claim
150 words
A method for forming an isolation structure of a semiconductor device, comprising the steps of: forming a first insulating film on a first portion of a substrate except for a field region; sequentially forming a second insulating film and a third insulating film over the entire exposed surface of the resulting structure; forming a side wall comprised of a part of the third insulating film on a portion of the second insulating film disposed over a second portion of the substrate corresponding to the field region; forming a field insulating film on a predetermined portion of the resulting structure corresponding to the field region using the side wall as a mask; removing the side wall; implanting channel stop ions in a third portion of the substrate corresponding to a region defined beneath the side wall; and annealing the implanted channel stop ions and thereby forming a channel stop diffusion region.
Claim 6
Independent Claim
150 words
A method for forming an isolation structure of a semiconductor device, comprising the steps of: forming a first insulating film on a first portion of a substrate except for a field region; sequentially forming a second insulating film and a third insulating film over the entire exposed surface of the resulting structure; forming a side wall comprised of a part of the third insulating film on a portion of the second insulating film disposed over a second portion of the substrate corresponding to the field region; forming a field insulating film on a predetermined portion of the resulting structure corresponding to the field region using the side wall as a mask; removing the side wall; implanting channel stop ions in a third portion of the substrate corresponding to a region defined beneath the side wall; and annealing the implanted channel stop ions and thereby forming a channel stop diffusion region.
Claim 7
Independent Claim
159 words
A method for forming an isolation structure of a semiconductor device, comprising the steps of: forming a first insulating film on a first portion of a substrate except for a field region; sequentially forming a second insulating film and a third insulating film over the entire exposed surface of the resulting structure; forming a side wall comprised of a part of the third insulating film on a portion of the second insulating film disposed over a second portion of the substrate corresponding to the field region; forming a field insulating film on a predetermined portion of the resulting structure corresponding to the field region using the side wall as a mask; removing the side wall; implanting channel stop ions in a third portion of the substrate corresponding to a region defined beneath the side wall; forming a planarizing layer along the field insulating film; and annealing the implanted channel stop ions and thereby forming a channel stop diffusion region.
Claim 8
Independent Claim
159 words
A method for forming an isolation structure of a semiconductor device, comprising the steps of: forming a first insulating film on a first portion of a substrate except for a field region; sequentially forming a second insulating film and a third insulating film over the entire exposed surface of the resulting structure; forming a side wall comprised of a part of the third insulating film on a portion of the second insulating film disposed over a second portion of the substrate corresponding to the field region; forming a field insulating film on a predetermined portion of the resulting structure corresponding to the field region using the side wall as a mask; removing the side wall; implanting channel stop ions in a third portion of the substrate corresponding to a region defined beneath the side wall; forming a planarizing layer along the field insulating film; and annealing the implanted channel stop ions and thereby forming a channel stop diffusion region.
Claim 9
Dependent Claim
46 words
The method in accordance with claim 5, wherein the step of forming the planarizing layer comprises the steps of depositing an insulating film over the entire exposed surface of the resulting structure obtained after forming the field insulating film, and then etching back the insulating film.
Claim 10
Dependent Claim
31 words
The method in accordance with claim 6, wherein the step of etching back the insulating film is carried out such that the planarizing layer is flush with the field insulating film.
Claim 11
Dependent Claim
17 words
The method in accordance with claim 5, wherein the planarizing layer is comprised of an oxide film.
Claim 12
Dependent Claim
30 words
The method in accordance with claim 5, wherein the planarizing layer is oxidized at the step of annealing the implanted channel stop ions to form the channel stop diffusion region.
Claim 13
Dependent Claim
18 words
The method in accordance with claim 9, wherein the planarizing layer is comprised of an amorphous silicon layer.
Claim 14
Dependent Claim
17 words
The method in accordance with claim 9, wherein the planarizing layer is comprised of a polysilicon layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-20 | 1999-05-22 | 1999-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-20 | 2003-05-22 | 2003-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-20 | 2007-05-22 | 2007-11-21 | $7700.00 | Window Closed / Lapsed |