High speed bus branches with compact physical spacing

Claim 2

A high speed peripheral bus for a computer system, comprising: a printed wiring board; a printed wiring conductor located on a first surface of said board, said printed wiring conductor being a single line of said high speed peripheral bus; a terminal of a first set of terminals connecting a first end of said printed wiring conductor to a high speed bus signal of said computer system; a terminal of a second set of terminals connecting to a second end of said printed wiring conductor; a terminal of a third set of terminals located between said terminal of said first set of terminals and said terminal of said second set of terminals connecting to said printed wiring conductor at a branch connection; and said printed wiring conductor being folded into a serpentine configuration between said terminal of said second set of terminals and a terminal of said third set of terminals to create a desired signal path length sufficient to reduce any reflection of said signal to a level that does not generate a false logic level.

Claim 3

The high speed peripheral bus for a computer system according to claim 1, further comprising: a distance between said terminal of said second set of terminals and said terminal of said third set of terminals is at most 0.05 meters.

Claim 4

A high speed peripheral bus for a computer system according to claim 2, further comprising: said path length of said signal between said terminal of said second set of terminals and said terminal of said third set of terminals is at least 0.3 meters.

Claim 5

A high speed peripheral bus for a computer system according to claim 1, further comprising: said path length of said signal between said terminal of said second set of terminals and said terminal of said third set of terminals is at least 0.3 meters.

Claim 6

A high speed peripheral bus for a computer system according to claim 4, further comprising: a ground conductor located on a second of said plurality of layers of said printed wiring board separated from said first layer by an insulating layer; and a characteristic impedance between said printed wiring conductor and said ground conductor is at least 90 ohms.

Claim 7

A high speed peripheral bus for a computer system according to claim 5, wherein said characteristic impedance is at the frequency of said signal.

Claim 8

A circuit apparatus to connect a plurality of signals of a high speed bus interface of a computer system, comprising: a printed wiring board; a first multiple conductor connector located on said printed wiring board for connecting to said plurality of signals of said high speed bus interface of said computer system; a first plurality of terminals located on said printed wiring board for connecting to said plurality of signals of said high speed bus interface of said computer system via said connector; a second multiple conductor connector mounted on said printed wiring board in a close spaced relationship to said first connector; a second plurality of terminals each connected to a respective conductor of said second multiple conductor connector; and a plurality of printed wiring conductors equal in number to said number of said plurality of signals of said high speed bus interface, each of said printed wiring conductors is connected between a respective terminal of said first plurality of terminals and a respective terminal of said second plurality of terminals, each of said printed wiring conductors having a serpentine shape so as to create a signal path length sufficient to reduce any signal reflection to a level that does not generate a false logic level.

Claim 9

A circuit apparatus to connect a plurality of signals of a high speed bus interface of a computer system, comprising: a printed wiring board; a first multiple conductor connector located on said printed wiring board for connecting to said plurality of signals of said high speed bus interface of said computer system; a first plurality of terminals located on said printed wiring board for connecting to said plurality of signals of said high speed bus interface of said computer system via said connector; a second multiple conductor connector mounted on said printed wiring board in a close spaced relationship to said first connector; a second plurality of terminals each connected to a respective conductor of said second multiple conductor connector; and a plurality of printed wiring conductors equal in number to said number of said plurality of signals of said high speed bus interface, each of said printed wiring conductors is connected between a respective terminal of said first plurality of terminals and a respective terminal of said second plurality of terminals, each of said printed wiring conductors having a serpentine shape so as to create a signal path length sufficient to reduce any signal reflection to a level that does not generate a false logic level.

Claim 10

A circuit apparatus as set forth in claim 7, wherein: each of said plurality of printed wiring conductors has a total length that is sufficient for any signal reflections caused by the connection to said second plurality of terminals to be reduced to an insignificant level.

Claim 11

A circuit apparatus as set forth in claim 8, wherein each of said plurality of printed wiring conductors has a total length of at least 0.3 meters.

Claim 12

A circuit apparatus as set forth in claim 9, wherein each of said plurality of printed wiring conductors has a characteristic impedance of at least 90 ohms.

Claim 13

A circuit apparatus as set forth in claim 10, wherein each of said plurality of printed wiring conductors has a total length of at least 0.3 meters folded in said serpentine shape within an area that is at most 0.05 meters in maximum extent.

Claim 14

A circuit apparatus as set forth in claim 11, wherein: each of said conductors is 0.0001524 meters in width; and an edge of one fold each of said conductors is located 0.0004826 meters from a nearest edge of an adjacent fold of said serpentine shape.

Claim 15

A circuit apparatus as set forth in claim 7, wherein: each of said conductors is spaced at least 0.005 meters from a nearest point of any other of said conductors.