US5466958A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS-type semiconductor device having electrode structure capable of coping with short-channel effect and manufacturing method thereof
Assignee: Toshiba Corp
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Filing: 1993-11-01
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Granted: 1995-11-14
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Expires: 2013-11-01
Abstract
Abstract In a semiconductor device, an n + polysilicon layer is formed on a substrate through a gateoxide layer. A p + source or drain diffusion layer is formed on both sides of an impurity layer in the substrate. The silicon layer positions over an intermediate portion of a channel formation layer, and has an oxide layer on upper surface thereof. The silicon layers have their side portions a p + type polysilicon layer to be a gate electrode together with the silicon layer. The gate electrode semiconductor layer is formed on the channel formation layer through the gate insulation layer in the manner that, in a portion contacting with the gate insulation layer, the nearer portions approaches to the impurity layers of the source and drain regions, the larger a work function increases.
Inventors
- 👤 Masakazu Kakumu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/605; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01322; H10D64/60; H10D64/66; H10D64/671; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/017; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
310 words
A semiconductor device comprising: a substrate formed of semiconductor having a first conductive type; an element dividing insulation layer that divides the substrate into element regions and insulation regions between the element regions; a gate insulation layer formed on the element regions; a channel formation layer disposed within an element region between the substrate and the gate insulation layer; a source electrode formed on one side of the channel formation layer and having a high concentration of impurities of a second conductivity type; a drain electrode formed on an other side of the channel formation layer and having a high concentration of impurities of the second conductivity type; said channel formation layer comprising a first impurity addition layer for preventing punch through positioned between the substrate and the gate insulation layer, said channel formation layer further comprising a second impurity addition layer positioned between the first impurity addition layer and the gate insulation layer, wherein the second impurity addition layer comprises a central portion for regulating a threshold voltage and being supplied a voltage in excess of the threshold value and edge portions which are supplied a voltage of a second predetermined value less than the threshold value; and a gate electrode formed on the gate insulation layer and including a first polysilicon layer having a high concentration of impurities of the first conductivity type and positioned at a portion corresponding to the center portion of the second impurity addition layer and an oxide layer stacked on the first polysilicon layer, the gate electrode further including second polysilicon layers having a high concentration of impurities of the second conductivity type and positioned along either side of the first polysilicon layer and the oxide layer, wherein the second polysilicon layers are positioned over portions of the source and drain electrodes and over the edge portions of the second impurity addition layer.
Claim 2
Dependent Claim
310 words
A semiconductor device comprising: a substrate formed of semiconductor having a first conductive type; an element dividing insulation layer that divides the substrate into element regions and insulation regions between the element regions; a gate insulation layer formed on the element regions; a channel formation layer disposed within an element region between the substrate and the gate insulation layer; a source electrode formed on one side of the channel formation layer and having a high concentration of impurities of a second conductivity type; a drain electrode formed on an other side of the channel formation layer and having a high concentration of impurities of the second conductivity type; said channel formation layer comprising a first impurity addition layer for preventing punch through positioned between the substrate and the gate insulation layer, said channel formation layer further comprising a second impurity addition layer positioned between the first impurity addition layer and the gate insulation layer, wherein the second impurity addition layer comprises a central portion for regulating a threshold voltage and being supplied a voltage in excess of the threshold value and edge portions which are supplied a voltage of a second predetermined value less than the threshold value; and a gate electrode formed on the gate insulation layer and including a first polysilicon layer having a high concentration of impurities of the first conductivity type and positioned at a portion corresponding to the center portion of the second impurity addition layer and an oxide layer stacked on the first polysilicon layer, the gate electrode further including second polysilicon layers having a high concentration of impurities of the second conductivity type and positioned along either side of the first polysilicon layer and the oxide layer, wherein the second polysilicon layers are positioned over portions of the source and drain electrodes and over the edge portions of the second impurity addition layer.
Claim 3
Dependent Claim
46 words
The semiconductor device according to claim 1, wherein said gate electrode layer is formed in the manner that the maximum value of the work function increases on or more 0.5 eV (electron volts) than the minimum value in a portion contacting with the gate insulation layer.
Claim 4
Dependent Claim
49 words
The semiconductor device according to claim 1, wherein said gate electrode layer comprises an n + -polysilicon layer which is formed on an intermediate region of the channel formation layer, and a p + -polysilicon layer which is formed as a side wall of the n + -polysilicon layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-11-13 | 1999-05-15 | 1999-11-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-11-13 | 2003-05-15 | 2003-11-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-11-13 | 2007-05-15 | 2007-11-14 | $7700.00 | Window Closed / Lapsed |