US5463759A
Expired / Lapsed
US
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Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system
Assignee: OPTi Inc
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Filing: 1995-04-10
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Granted: 1995-10-31
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Expires: 2015-04-10
Abstract
Abstract Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.
Inventors
- 👤 Subir K. Ghosh
- 👤 Dipankar Bhattacharya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:48
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0888; G06F12/0891; G06F12/0215
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
105 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, comprising the steps of: writing said data to said cache memory; determining whether said cache hit write access is also a DRAM page hit write access; writing said data through to said DRAM memory only if said cache hit write access is also a DRAM page hit write access; and flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access.
Claim 2
Independent Claim
105 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, comprising the steps of: writing said data to said cache memory; determining whether said cache hit write access is also a DRAM page hit write access; writing said data through to said DRAM memory only if said cache hit write access is also a DRAM page hit write access; and flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access.
Claim 3
Dependent Claim
43 words
A method according to claim 1, wherein said memory subsystem is such that on a cache read miss with a dirty condition flagged, information from said cache memory is written to said main memory before said cache read miss operation can be satisfied.
Claim 4
Independent Claim
156 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: writing said data to said cache memory; determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; writing said data through to said DRAM memory only if said cache hit write access is also a DRAM page hit write access and said RAS# signal is active; flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access; and flagging a dirty condition in said cache memory also if said RAS# signal is inactive.
Claim 5
Independent Claim
156 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: writing said data to said cache memory; determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; writing said data through to said DRAM memory only if said cache hit write access is also a DRAM page hit write access and said RAS# signal is active; flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access; and flagging a dirty condition in said cache memory also if said RAS# signal is inactive.
Claim 6
Independent Claim
189 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: writing said data to said cache memory; determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; determining whether a refresh of said DRAM is pending; writing said data through to said DRAM memory only if said cache hit write access is also a DRAM page hit write access, said RAS# signal is active, and no refresh of said DRAM is pending; flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access; flagging a dirty condition in said cache memory also if said RAS# signal is inactive; and flagging a dirty condition in said cache memory also if a refresh of said DRAM is pending.
Claim 7
Independent Claim
189 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: writing said data to said cache memory; determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; determining whether a refresh of said DRAM is pending; writing said data through to said DRAM memory only if said cache hit write access is also a DRAM page hit write access, said RAS# signal is active, and no refresh of said DRAM is pending; flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access; flagging a dirty condition in said cache memory also if said RAS# signal is inactive; and flagging a dirty condition in said cache memory also if a refresh of said DRAM is pending.
Claim 8
Independent Claim
155 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: writing said data to said cache memory; determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; writing said data through to said DRAM memory if said cache hit write access is also a DRAM page hit write access; writing said data through to said DRAM memory also if said RAS# signal is inactive; and flagging a dirty condition in said cache memory only if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active.
Claim 9
Independent Claim
155 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: writing said data to said cache memory; determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; writing said data through to said DRAM memory if said cache hit write access is also a DRAM page hit write access; writing said data through to said DRAM memory also if said RAS# signal is inactive; and flagging a dirty condition in said cache memory only if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active.
Claim 10
Independent Claim
195 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: writing said data to said cache memory; determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; determining whether a refresh of said DRAM is pending; writing said data through to said DRAM memory if said cache hit write access is also a DRAM page hit write access and no refresh of said DRAM is pending; writing said data through to said DRAM memory also if said RAS# signal is inactive and no refresh of said DRAM is pending; flagging a dirty condition in said cache memory if said cache hit write access is not a DRAM page hit write access and said RAS#signal is active; and flagging a dirty condition in said cache memory also if a refresh of said DRAM is pending.
Claim 11
Independent Claim
195 words
A method for writing data to a memory subsystem on a cache hit write access, said memory subsystem including a cache memory, a page mode DRAM memory and memory subsystem control apparatus, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory subsystem control apparatus, comprising the steps of: writing said data to said cache memory; determining whether said cache hit write access is also a DRAM page hit write access; determining whether said RAS# signal is active; determining whether a refresh of said DRAM is pending; writing said data through to said DRAM memory if said cache hit write access is also a DRAM page hit write access and no refresh of said DRAM is pending; writing said data through to said DRAM memory also if said RAS# signal is inactive and no refresh of said DRAM is pending; flagging a dirty condition in said cache memory if said cache hit write access is not a DRAM page hit write access and said RAS#signal is active; and flagging a dirty condition in said cache memory also if a refresh of said DRAM is pending.
Claim 12
Dependent Claim
121 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, for use in response to a cache hit data write access, comprising: means for writing said data to said cache memory; first determining means for determining whether said cache hit write access is also a DRAM page hit write access; means, responsive to said first determining means, for writing said data through to said DRAMmemory only if said cache hit write access is also a DRAM page hit write access; and means, responsive to said first determining means, for flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access.
Claim 13
Dependent Claim
121 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, for use in response to a cache hit data write access, comprising: means for writing said data to said cache memory; first determining means for determining whether said cache hit write access is also a DRAM page hit write access; means, responsive to said first determining means, for writing said data through to said DRAMmemory only if said cache hit write access is also a DRAM page hit write access; and means, responsive to said first determining means, for flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access.
Claim 14
Dependent Claim
186 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, for use in response to a cache hit data write access, comprising: means for writing said data to said cache memory; first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; means, responsive to said first and second determining means, for writing said data through to said DRAM memory only if said cache hit write access is also a DRAM page hit write access and said RAS# signal is active; means, responsive to said first determining means, for flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access; and means, responsive to said second determining means, for flagging a dirty condition in said cache memory also if said RAS# signal is inactive.
Claim 15
Dependent Claim
186 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, for use in response to a cache hit data write access, comprising: means for writing said data to said cache memory; first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; means, responsive to said first and second determining means, for writing said data through to said DRAM memory only if said cache hit write access is also a DRAM page hit write access and said RAS# signal is active; means, responsive to said first determining means, for flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access; and means, responsive to said second determining means, for flagging a dirty condition in said cache memory also if said RAS# signal is inactive.
Claim 16
Dependent Claim
221 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, comprising: means for writing said data to said cache memory; first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; third determining means for determining whether a refresh of said DRAM is pending; means, responsive to said first, second and third determining means, for writing said data through to said DRAM memory only if said cache hit write access is also a DRAM page hit write access, said RAS# signal is active, and no refresh of said DRAM is pending; means, responsive to said first determining means, for flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access; means, responsive to said second determining means, for flagging a dirty condition in said cache memory also if said RAS# signal is inactive; and means, responsive to said third determining means, for flagging a dirty condition in said cache memory also if a refresh of said DRAM is pending.
Claim 17
Dependent Claim
221 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, comprising: means for writing said data to said cache memory; first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; third determining means for determining whether a refresh of said DRAM is pending; means, responsive to said first, second and third determining means, for writing said data through to said DRAM memory only if said cache hit write access is also a DRAM page hit write access, said RAS# signal is active, and no refresh of said DRAM is pending; means, responsive to said first determining means, for flagging a dirty condition in said cache memory if said cache hit write access is not also a DRAM page hit write access; means, responsive to said second determining means, for flagging a dirty condition in said cache memory also if said RAS# signal is inactive; and means, responsive to said third determining means, for flagging a dirty condition in said cache memory also if a refresh of said DRAM is pending.
Claim 18
Dependent Claim
177 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, for use in response to a cache hit data write access, comprising: means for writing said data to said cache memory; first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; means, responsive to said first determining means, for writing said data through to said DRAM memory if said cache hit write access is also a DRAM page hit write access; means, responsive to said second determining means, for writing said data through to said DRAM memory also if said RAS# signal is inactive; and means for flagging a dirty condition in said cache memory only if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active.
Claim 19
Dependent Claim
177 words
Memory management apparatus for use with a memory subsystem having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, for use in response to a cache hit data write access, comprising: means for writing said data to said cache memory; first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAS# signal is active; means, responsive to said first determining means, for writing said data through to said DRAM memory if said cache hit write access is also a DRAM page hit write access; means, responsive to said second determining means, for writing said data through to said DRAM memory also if said RAS# signal is inactive; and means for flagging a dirty condition in said cache memory only if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active.
Claim 20
Dependent Claim
238 words
Memory management apparatus for use with a memory having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, for use in response to a cache hit write data access, comprising: means for writing said data to said cache memory; first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAg# signal is active; third determining means for determining whether a refresh of said DRAM is pending; means, responsive to said first and third determining means, for writing said data through to said DRAMmemory if said cache hit write access is also a DRAMpage hit write access and no refresh of said DRAM is pending; means, responsive to said second and third determining means, for writing said data through to said DRAMmemory also if said RAS# signal is inactive and no refresh of said DRAM is pending; means, responsive to said first and second determining means, for flagging a dirty condition in said cache memory if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active; and means, responsive to said third determining means, for flagging a dirty condition in said cache memory also if a refresh of said DRAM is pending.
Claim 21
Dependent Claim
238 words
Memory management apparatus for use with a memory having a cache memory and a page mode DRAM memory, said DRAM memory having a row address strobe (RAS#) input coupled to receive a RAS# signal provided by said memory management apparatus, for use in response to a cache hit write data access, comprising: means for writing said data to said cache memory; first determining means for determining whether said cache hit write access is also a DRAM page hit write access; second determining means for determining whether said RAg# signal is active; third determining means for determining whether a refresh of said DRAM is pending; means, responsive to said first and third determining means, for writing said data through to said DRAMmemory if said cache hit write access is also a DRAMpage hit write access and no refresh of said DRAM is pending; means, responsive to said second and third determining means, for writing said data through to said DRAMmemory also if said RAS# signal is inactive and no refresh of said DRAM is pending; means, responsive to said first and second determining means, for flagging a dirty condition in said cache memory if said cache hit write access is not a DRAM page hit write access and said RAS# signal is active; and means, responsive to said third determining means, for flagging a dirty condition in said cache memory also if a refresh of said DRAM is pending.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-30 | 1999-05-01 | 1999-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-30 | 2003-05-01 | 2003-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-30 | 2007-05-01 | 2007-10-31 | $7700.00 | Window Closed / Lapsed |