Fuzzy microcontroller

Claim 2

A fuzzy logic microcontroller for controlling a device in response to at least one crisp input signal, comprising: means for mapping said crisp input signal to at least one fuzzy set, each fuzzy set having a membership function having a predetermined width and a center, means for fuzzifying said crisp input signal to obtain fuzzified input signals, said fuzzifying means comprising: means for determining a distance of said crisp input from said center of each of said membership functions, and means for linearly complementing each of said distances relative to said corresponding width of said membership function in accordance with a polarity of said membership function, said complemented distance being output as said fuzzified input signal; means for executing an optimized rule in accordance with said fuzzified input signals, said optimized rule being selected from a plurality of predetermined rules each having rule terms, said executing means comprising: means for determining a minimum rule term in accordance with said fuzzified input signals and a selected one of said predetermined rules, said selected rule being part of a group of rules corresponding to a control output; means for determining a maximum rule term among said minimum rule terms of said group of rules; and means for outputting an action value of said optimal rule corresponding to said maximum rule term as an output signal for said device to be controlled.

Claim 3

A fuzzy logic microcontroller as recited in claim 1, wherein said means for fuzzifying further includes means for supplying a selected input as said center of said membership function.

Claim 4

A fuzzy logic microcontroller as recited in claim 2, further comprising a timer processor for generating a time-variable signal, said time-variable signal being selected as said center of said membership function.

Claim 5

A fuzzy logic microcontroller as recited in claim 1, wherein said device is controlled in response to a plurality of time-division-multiplexed crisp input signals.

Claim 6

A fuzzy logic microcontroller as recited in claim 4, wherein said mapping means comprises: means for demultiplexing said time-division crisp input signals in response to a multiplexer address signal; and a selector circuit for supplying one of said demultiplexed input signals to said means for fuzzifying.

Claim 7

A fuzzy microcontroller as recited in claim 1, wherein said fuzzy microcontroller is operated in a master mode with an external memory.

Claim 8

A fuzzy microcontroller as recited in claim 1, wherein said fuzzy microcontroller is operated in a slave mode with a microprocessor.

Claim 9

A fuzzy logic microcontroller for controlling a device in response to at least one crisp input signal, said fuzzy logic microcontroller comprising: means for mapping said crisp input signal to at least one fuzzy set, each fuzzy set having a membership function having a predetermined width and a center; means for fuzzifying said crisp input signal to obtain fuzzified input signals, said fuzzifying means comprising: means for determining a distance of said crisp input from said center of each of said membership functions, and means for linearly complementing each of said distances relative to said corresponding width of said membership function in accordance with a polarity of said membership function, said complemented distance being output as said fuzzified input signal; and means for executing an optimized rule in accordance with said fuzzified input signals, said optimized rule being selected from a plurality of predetermined rules each having rule terms, said executing means comprising: means for determining a minimum rule term in accordance with said fuzzified input signals and a selected one of said predetermined rules, said selected rule being part of a group of rules corresponding to a control output, means for determining a maximum rule term among a plurality of said minimum rule terms corresponding to said group of rules, means for outputting an action value of said optimal rule corresponding to said maximum rule term as an output signal for said device to be controlled, a keyboard controller for controlling an external keyboard in accordance with one of said rules being processed, said keyboard controller outputting a match signal to said means for determining a minimum rule term, and means for outputting said action value in accordance with a rule mode of said optimized rule.

Claim 10

A fuzzy logic microcontroller for controlling a device in response to at least one crisp input signal, said fuzzy logic microcontroller comprising: means for mapping said crisp input signal to at least one fuzzy set, each fuzzy set having a membership function having a predetermined width and a center; means for fuzzifying said crisp input signal to obtain fuzzified input signals, said fuzzifying means comprising: means for determining a distance of said crisp input from said center of each of said membership functions, and means for linearly complementing each of said distances relative to said corresponding width of said membership function in accordance with a polarity of said membership function, said complemented distance being output as said fuzzified input signal; and means for executing an optimized rule in accordance with said fuzzified input signals, said optimized rule being selected from a plurality of predetermined rules each having rule terms, said executing means comprising: means for determining a minimum rule term in accordance with said fuzzified input signals and a selected one of said predetermined rules, said selected rule being part of a group of rules corresponding to a control output, means for determining a maximum rule term among a plurality of said minimum rule terms corresponding to said group of rules, means for outputting an action value of said optimal rule corresponding to said maximum rule term as an output signal for said device to be controlled, a keyboard controller for controlling an external keyboard in accordance with one of said rules being processed, said keyboard controller outputting a match signal to said means for determining a minimum rule term, and means for outputting said action value in accordance with a rule mode of said optimized rule.

Claim 11

A fuzzy logic microcontroller as recited in claim 1, further comprising a timing generator for outputting a multiplexer address signal defining an I/O timeslot, said multiplexer address signal being output in accordance with a number of fuzzifiers and a number of rules to be processed for controlling said means for fuzzifying and said means for executing.

Claim 12

A fuzzy logic microcontroller as recited in claim 1, wherein said means for determining a minimum rule term includes a multipath feedforward network comprising: a plurality of minimizing elements corresponding to said fuzzy sets, respectively, said minimizing elements each receiving said corresponding fuzzified input signals in accordance with said selected one of said rules and a feedback signal, each of said minimizing elements outputting a minimum output signal, said minimum output signal having lower order bits disabled when a corresponding significant bit of said input signal is different from a corresponding significant bit of said feedback signal indicating said feedback signal has a value less than a corresponding value of said input signal; and means for successively comparing corresponding significant bits of said minimum output signals of said respective minimizing elements and outputting said feedback signal in response thereto, said feedback signal representing, upon stabilization of said multipath feedforward network, said minimum rule term of said selected rule.

Claim 13

A fuzzy logic microcontroller as recited in claim 10, wherein each of said minimizing elements comprises: a first network layer for comparing corresponding significant bits of said corresponding fuzzified input signal and said feedback signal, said first network layer outputting a disabling signal for said lower order bits when said corresponding significant bit of said fuzzified input signal is different from said corresponding bit of said feedback signal; and an output network layer for outputting said compared bits of said corresponding fuzzified input signal as said minimum output signal in accordance with said disabling signal and a rule-based disable signal supplied in accordance with said selected rule, said output network layer outputting said fuzzified input signal if, upon said stabilization, said output network layer has not received said disabling signal.

Claim 14

A fuzzy logic microcontroller as recited in claim 11, wherein said means for successively comparing comprises a plurality of NAND gates corresponding to each significant bit of said minimum output signals of said minimizing elements, each of said NAND gates outputting a corresponding significant bit of said feedback signal, said NAND gates determining a difference in value in said respective significant bits of said minimum output signals.

Claim 15

A fuzzy logic microcontroller as recited in claim 10, wherein said means for successively comparing comprises a plurality of NAND gates corresponding to each significant bit of said minimum output signals of said minimizing elements, each of said NAND gates outputting a corresponding significant bit of said feedback signal, said NAND gates determining a difference in value in said respective significant bits of said minimum output signals.