Address decision system having address check system

Claim 2

An address decision system in an Asynchronous Transfer Mode (ATM) exchange, comprising: table memory means for storing data showing relationships between Virtual Path Identifier/Virtual Channel Identifier (VPI/VCI) values and addresses; latch means, coupled to a cell highway, for latching a VPI/VCI value contained in a cell transferred via the cell highway; comparator means, coupled to said table memory means and said latch means, for comparing the VPI/VCI values stored in the table memory means with the VPI/VCI value latched by said latch means and for generating a comparator output signal designating, in a normal operation, one of the addresses at which the VPI/VCI value from said latch means coincides with one of the VPI/VCI values in said table memory means; encoding means, coupled to said comparator means, for encoding the comparator output signal and thereby generating an encoded signal, based on the comparator output signal, as the output thereof; and check means comprising: decoder means, coupled to said encoding means, for decoding the encoded signal and generating a decoded signal; and error checking means, coupled to said comparator means and said decoder means, for receiving the comparator output signal and the decoded signal and for generating an error signal when the comparator output signal and the decoded signal do not match each other.

Claim 3

An address decision system as claimed in claim 1, wherein: n represents a value and m represents a value; the comparator output signal comprises n bits respectively related to the addresses of said table memory means, and the encoded signal comprises m bits where m is smaller than n; and said encoding means comprises logic means for executing a predetermined encoding operation based on a relationship between the value of n and the value of m and for generating the encoded signal comprising m bits and indicating one of the addresses at which the VPI/VCI value from said latch means coincides with one of the VPI/VCI values in said table memory means.

Claim 4

An address decision system as claimed in claim 1, wherein: the comparator output signal comprises n bits respectively related to the addresses of said table memory means; and said comparator means comprises means for setting one of said n bits to a first value, said one of the n bits corresponding to one of the addresses at which the VPI/VCI value from said latch means coincides with one of the VPI/VCI values in said table memory means and for respectively setting remaining bits (n-1) to a second value.

Claim 5

An address decision system as claimed in claim 3, wherein said check means comprises: means for determining whether or not a plurality of bits among the n bits from said comparator means are respectively equal to the first value; and means for generating the error signal when said plurality of bits among the n bits from said comparator means are respectively equal to the first value.

Claim 6

An address decision system as claimed in claim 3, wherein said check means comprises: means for determining whether an error which causes all the n bits from the comparator means to be the second value exists; and means for generating a second error signal in response to detection of the error which causes all the n bits from the comparator means to be the second value has occurred.

Claim 7

An address decision system as claimed in claim 1, wherein: m is a value and n is a value; the comparator output signal comprises n bits respectively related to the addresses of said table memory means; the encoded signal comprises m bits where m is smaller than n; and said encoding means comprises: m first logic gates coupled to said comparator means for realizing said predetermined bits among the n bits from the comparator means in accordance with said predetermined encoding operation and outputting respective output signals; m second logic gates respectively having first terminals for receiving a predetermined one of the n bits from the comparator means, second terminals for receiving the respective output signals of said m first logic gates and outputting m output signals; and m output signals of said m second logic gates forming the encoded signal.

Claim 8

An address decision system as claimed in claim 6, wherein said check means comprises: first means for decoding the m output signals of said m second logic gates into a decoded address signal including n bits; and second means, coupled to said first means, for comparing the decoded address signal to said comparator output signal and for generating said error signal when the comparator output signal and the decoded address signal coincide with each other.

Claim 9

An address decision system as claimed in claim 7, wherein said check means comprises third means for receiving said predetermined one of the n bits from the comparator means and said m output signals of said m first logic gates and for generating another error signal based on said predetermined one of the n bits from the comparator means and said m output signals of said m first logic gates.

Claim 10

An address decision system as claimed in claim 8, wherein said third means comprises: an inverter for inverting said predetermined one of the n bits from the comparator means; and an OR gate for receiving an output signal of said inverter and said m output signals of said m first logic gates and generating said a second error signal.

Claim 11

An address decision system as claimed in claim 6, wherein: said m first logic gates respectively comprise NAND gates; and said m second logic gates respectively comprise AND gates.

Claim 12

An address decision system in a system which transfers packets having a fixed length, comprising: table memory means for storing data showing relationships between channel identification values and addresses; latch means, coupled to a cell highway, for latching a channel identification value contained in a cell transferred via the cell highway; comparator means, coupled to said table memory means and said latch means, for comparing the channel identification values stored in the table memory means with the channel identification value latched by said latch means and for generating a comparator output signal designating, in a normal operation, one of the addresses at which the channel identification value from said latch means coincides with one of the channel identification values in said table memory means; encoding means, coupled to said comparator means, for encoding the comparator output signal and thereby generating an encoded signal, based on the comparator output signal, as the output thereof; and check means comprising: decoder means, coupled to said encoding means, for decoding the encoded signal and generating a decoded signal; and error checking means, coupled to said comparator means and said decoder means, for receiving the comparator output signal and the decoded signal and for generating an error signal when the comparator output signal and the decoded signal do not match each other.

Claim 13

An address decision system in a system which transfers packets having a fixed length, comprising: table memory means for storing data showing relationships between channel identification values and addresses; latch means, coupled to a cell highway, for latching a channel identification value contained in a cell transferred via the cell highway; comparator means, coupled to said table memory means and said latch means, for comparing the channel identification values stored in the table memory means with the channel identification value latched by said latch means and for generating a comparator output signal designating, in a normal operation, one of the addresses at which the channel identification value from said latch means coincides with one of the channel identification values in said table memory means; encoding means, coupled to said comparator means, for encoding the comparator output signal and thereby generating an encoded signal, based on the comparator output signal, as the output thereof; and check means comprising: decoder means, coupled to said encoding means, for decoding the encoded signal and generating a decoded signal; and error checking means, coupled to said comparator means and said decoder means, for receiving the comparator output signal and the decoded signal and for generating an error signal when the comparator output signal and the decoded signal do not match each other.

Claim 14

An address decision system as claimed in claim 11, wherein said system which transfers packets having a fixed length is an Asynchronous Transfer Mode Exchange, and wherein said channel identification values are Virtual Path Identifier/Virtual Channel Identifier values.