Method for making capacitor for use in DRAM cell using triple layers of photoresist

Claim 1

A method for forming a capacitor for use in a DRAM cell, comprising the steps of: (a) forming a polysilicon electrode layer on a substrate; (b) forming an oxide layer on the polysilicon electrode layer; (c) forming a plurality of spaced apart oxide regions from said oxide layer by: (i) patterning a first photoresist layer to form spaced apart photoresist regions; (ii) etching the oxide layer through the patterned first photoresist layer; (iii) forming a subsequent photoresist layer to form spaced apart photoresist regions, the subsequent layer being shifted a first amount from the first photoresist layer; (iv) etching the oxide layer through the patterned subsequent layer; and (v) repeating steps iii and iv such that a plurality of spaced apart oxide regions are formed wherein the width of each oxide region is significantly smaller than the width of each said photoresist region; and (d) using said oxide regions as a mask, etching said polysilicon electrode layer to form pillars therein.

Claim 2

A method for forming a capacitor for use in a DRAM cell, comprising the steps of: (a) forming a polysilicon electrode layer on a substrate; (b) forming an oxide layer on the polysilicon electrode layer; (c) forming a plurality of spaced apart oxide regions from said oxide layer by: (i) patterning a first photoresist layer to form spaced apart photoresist regions; (ii) etching the oxide layer through the patterned first photoresist layer; (iii) forming a subsequent photoresist layer to form spaced apart photoresist regions, the subsequent layer being shifted a first amount from the first photoresist layer; (iv) etching the oxide layer through the patterned subsequent layer; and (v) repeating steps iii and iv such that a plurality of spaced apart oxide regions are formed wherein the width of each oxide region is significantly smaller than the width of each said photoresist region; and (d) using said oxide regions as a mask, etching said polysilicon electrode layer to form pillars therein.

Claim 4

A method for forming a capacitor for use in a DRAM cell, comprising the steps of: (a) forming a polysilicon electrode layer on a substrate; (b) forming an insulating layer having a depth on the polysilicon electrode layer; (c) patterning a first photoresist layer defining a number of first spaces, the first spaces having a width; (d) etching one-half of the depth of the exposed insulating layer; (e) patterning a second photoresist layer defining a number of second spaces having the width, locating the second photoresist layer to align the spaces two-thirds the width in a first direction away from the first spaces; (f) etching one-half of the depth of the insulation layer exposed by the second photoresist layer; (g) patterning a third photoresist layer defining third spaces having the width, locating the third photoresist layer to align the spaces two-thirds the width in a second direction opposite the first direction away from the first spaces; (h) etching one-half of the depth of the insulation layer exposed by the third photoresist layer; (i) using the insulating regions as a mask, etching said polysilicon electrode layer to form pillars therein; (j) forming a dielectric layer on the polysilicon electrode layer; and (k) forming a second polysilicon electrode layer on the dielectric layer.

Claim 5

A method for forming a capacitor for use in a DRAM cell, comprising the steps of: (a) forming a polysilicon electrode layer on a substrate; (b) forming an insulating layer having a depth on the polysilicon electrode layer; (c) patterning a first photoresist layer defining a number of first spaces, the first spaces having a width; (d) etching one-half of the depth of the exposed insulating layer; (e) patterning a second photoresist layer defining a number of second spaces having the width, locating the second photoresist layer to align the spaces two-thirds the width in a first direction away from the first spaces; (f) etching one-half of the depth of the insulation layer exposed by the second photoresist layer; (g) patterning a third photoresist layer defining third spaces having the width, locating the third photoresist layer to align the spaces two-thirds the width in a second direction opposite the first direction away from the first spaces; (h) etching one-half of the depth of the insulation layer exposed by the third photoresist layer; (i) using the insulating regions as a mask, etching said polysilicon electrode layer to form pillars therein; (j) forming a dielectric layer on the polysilicon electrode layer; and (k) forming a second polysilicon electrode layer on the dielectric layer.