Efficient switched mode power converter circuit and method

Claim 3

The method of claim 1 wherein said disabling step further comprises the step of: occasionally disabling the synchronous rectifier during approximately one off-period of the switching signal, corresponding to one discharge period of the inductor.

Claim 4

The method of claim 1 wherein said detecting step occurs near the conclusion of an off-period of the switching signal.

Claim 5

The method of claim 1 wherein said detecting step occurs near the conclusion of an off-period of the switching signal; and wherein said disabling step further comprises the step of occasionally disabling the synchronous rectifier during approximately one off-period of the switching signal.

Claim 6

The method of claim 1 wherein said disabling step further comprises the steps of: occasionally extending the length of the off-period of a first cycle of the switching signal by a first duration; and disabling the synchronous rectifier during said first duration; said method further comprising the step of: reducing the length of the off-period of a second cycle of the switching signal by said first duration, wherein the second cycle is adjacent to the first cycle; and said repeating step further comprising the step of repeating said reducing step.

Claim 7

The method of claim 5 wherein said detecting step occurs near the conclusion of said first duration.

Claim 8

The method of claim 1 wherein said disabling step further comprises the steps of: occasionally extending the length of the off-period of a first cycle of the switching signal by a first duration; further extending the length of the off-period of the first cycle by a second duration if the synchronous rectifier was disabled during the cycle immediately preceding the first cycle; disabling the synchronous rectifier during the duration that the off-period of the first cycle has been extended; said method further comprising the steps of: reducing the length of the off-period of a second cycle of the switching signal by the first duration, wherein the second cycle is adjacent to the first cycle; further reducing the length of the off-period of the second cycle by the second duration if the synchronous rectifier was disabled during the cycle immediately preceding the first cycle; and wherein said repeating step further comprises repeating said reducing step and said further reducing step.

Claim 9

The method of claim 7 wherein said detecting step occurs near the conclusion of the duration that the off-period of the first cycle has been extended.

Claim 10

A synchronous rectifier disabler circuit for use with a switched-mode power converter including at least one synchronous rectifier capable of being enabled or disabled and coupled to an inductor, a control circuit operable to generate a cyclical switching signal having an on-period and an off-period during each cycle, the off-period corresponding to the discharge period of the inductor, and a diode rectifier operable to provide a current path for the inductor current when the synchronous rectifier is disabled and block reverse current flow in the inductor, comprising: a test pulse generator coupled to the control circuit and operable to receive the switching signal and generate a test pulse in response to the switching signal; a mode sensor coupled to the inductor and operable to generate a power level signal having at least two possible values wherein a first value of the power level signal indicates that the power converter is operating at a power level above a selected threshold and wherein a second value of the power level signal indicates that the power converter is operating at a power level below the selected threshold, the mode sensor further operable to generate the power level signal by sensing a voltage representative of the energy stored in the inductor and by comparing the energy stored in the inductor to a reference energy; a mode memory coupled to said mode sensor and operable to sample and store the value of the power level signal in response to said test pulse and produce a memory output equivalent to the stored value; and a rectifier controller coupled to said test pulse generator, said mode memory, the control circuit, and the synchronous rectifier and operable to disable the synchronous rectifier in response to the test pulse, disable the synchronous rectifier in response to the switching signal, and disable the synchronous rectifier when said memory output equals the second value of the power level signal.

Claim 11

A synchronous rectifier disabler circuit for use with a switched-mode power converter including at least one synchronous rectifier capable of being enabled or disabled and coupled to an inductor, a control circuit operable to generate a cyclical switching signal having an on-period and an off-period during each cycle, the off-period corresponding to the discharge period of the inductor, and a diode rectifier operable to provide a current path for the inductor current when the synchronous rectifier is disabled and block reverse current flow in the inductor, comprising: a test pulse generator coupled to the control circuit and operable to receive the switching signal and generate a test pulse in response to the switching signal; a mode sensor coupled to the inductor and operable to generate a power level signal having at least two possible values wherein a first value of the power level signal indicates that the power converter is operating at a power level above a selected threshold and wherein a second value of the power level signal indicates that the power converter is operating at a power level below the selected threshold, the mode sensor further operable to generate the power level signal by sensing a voltage representative of the energy stored in the inductor and by comparing the energy stored in the inductor to a reference energy; a mode memory coupled to said mode sensor and operable to sample and store the value of the power level signal in response to said test pulse and produce a memory output equivalent to the stored value; and a rectifier controller coupled to said test pulse generator, said mode memory, the control circuit, and the synchronous rectifier and operable to disable the synchronous rectifier in response to the test pulse, disable the synchronous rectifier in response to the switching signal, and disable the synchronous rectifier when said memory output equals the second value of the power level signal.

Claim 12

The synchronous rectifier disabler circuit of claim 9 wherein the test pulse generator is operable to generate the test pulse periodically after each occurrence of a fixed plurality of cycles of the switching signal.

Claim 13

The synchronous rectifier disabler circuit of claim 9 wherein said mode memory is operable to sample and store the value of the power level signal at a transition edge of said test pulse.

Claim 14

The synchronous rectifier disabler circuit of claim 9 wherein the test pulse generator is operable to generate a test pulse having a duration approximately equal to one cycle of the switching signal and wherein said rectifier controller is operable to disable the synchronous rectifier for the duration of the test pulse.

Claim 15

The synchronous rectifier disabler circuit of claim 9 wherein said test pulse generator further comprises: a delay circuit coupled to the control circuit and responsive to a first gate signal having at least a first enable value and a first disable value, said delay circuit operable to produce a delay output comprising the switching signal when the first gate signal is equal to the first disable value, and comprising the switching signal delayed by a first duration when the first gate signal has the first enable value; a pulse circuit coupled to said delay circuit and operable to receive the delay output and occasionally generate a test pulse in response thereto, wherein the test pulse comprises the first gate signal; and wherein said rectifier controller is also coupled to said delay circuit and operable to receive the delay output, wherein said rectifier controller is operable to disable the synchronous rectifier in response to the test pulse for the duration that the switching signal differs in value from the delay output during an off-period of the delay output.

Claim 16

The synchronous rectifier disabler circuit of claim 13 wherein said pulse circuit is operable to generate the test pulse periodically after each occurrence of a fixed plurality of cycles of the delay output.

Claim 17

The synchronous rectifier disabler circuit of claim 13 wherein said mode memory is operable to sample and store the value of the power level signal at a transition edge of said test pulse.

Claim 18

The synchronous rectifier disabler circuit of claim 9 wherein said test pulse generator further comprises: a delay circuit coupled to the control circuit, responsive to a first gate signal having at least a first enable value and a first disable value, further responsive to a second gate signal having at least a second enable value and a second disable value and operable to produce a delay output comprising the switching signal when the first gate signal has the first disable value and comprising the switching signal delayed by a first duration when the first gate signal has the first enable value and the second gate signal has the second disable value, and comprising the switching signal delayed by a second duration when the first gate signal has the first enable value and the second gate signal has the second enable value; a pulse circuit coupled to said delay circuit and operable to receive the delay output and occasionally generate a test pulse in response thereto and wherein the test pulse comprises the first gate signal; wherein said memory output serves as the second gate signal; and wherein said rectifier controller is also coupled to said delay circuit and operable to receive the delay output and wherein said rectifier controller is operable to disable the synchronous rectifier in response to the test pulse for the duration that the switching signal differs in value from the delay output during an off-period of the delay output.

Claim 19

The synchronous rectifier disabler circuit of claim 16 wherein said pulse circuit is operable to generate the test pulse periodically after each occurrence of a fixed plurality of cycles of the delay output.

Claim 20

The synchronous rectifier disabler circuit of claim 16 wherein said mode memory is operable to sample and store the value of the power level signal at a transition edge of said test pulse.

Claim 21

The synchronous rectifier disabler circuit of claim 9 wherein said mode memory is a flip-flop that is operable to sample and store the value of the power level signal at a transition edge of said test pulse.

Claim 22

The synchronous rectifier disabler circuit of claim 9 wherein the test pulse generator comprises a counter that is operable to generate the test pulse periodically after each occurrence of a fixed plurality of cycles of the switching signal and wherein the test pulse has a duration approximately equal to the duration of one cycle of the switching signal.