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US5457429A Expired / Lapsed US ⏱️ 0.0 years remaining

Ring oscillator circuit for VCO

Assignee: Sony Corp
•
Filing: 1994-08-15
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Granted: 1995-10-10
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Expires: 2014-08-15
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Abstract

Abstract In a ring oscillator type VCO in which plural stages of inverter circuits are cascade-connected to each other so as to constitute a positive feedback loop, delay amounts for both a rising edge and a falling edge of an output signal from the inverter circuit are controlled to have the same delay amount by way of a control signal. These delay amounts of the rising edge and the falling edge are controllable in such a manner that the duty ratio of an oscillator output signal is not varied. Each stage of the inverter circuit is arranged by three-stage inverters made of load transistors and driver transistors, and the control voltage is applied to the load transistors of the two adjoining inverters among the three-stage inverters.

Inventors

  • 👤 Akihide Ogawa
  • 👤 Kazuhiro Takeda
  • 👤 Masami Goseki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 19:02
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0315; H03K3/353; H03K3/354

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 138 words
A ring oscillator circuit comprising: an even number of cascade-connected first inverters each having a first transistor and a second transistor series-connected to said first transistor, in which an input signal Vin is applied to an input terminal of one of said first and second transistors, a control signal Vc is supplied to an input terminal of the other of said first and second transistors, and outputs of said first and second transistors are commonly connected to each other; and a second inverter having a third transistor and a fourth transistor series-connected to said third transistor, in which input terminals of said third and fourth transistors to which an output signal from said first inverter is inputted are commonly connected to each other, and output terminals of said third and fourth transistors are commonly connected to each other.
Claim 2
Dependent Claim 138 words
A ring oscillator circuit comprising: an even number of cascade-connected first inverters each having a first transistor and a second transistor series-connected to said first transistor, in which an input signal Vin is applied to an input terminal of one of said first and second transistors, a control signal Vc is supplied to an input terminal of the other of said first and second transistors, and outputs of said first and second transistors are commonly connected to each other; and a second inverter having a third transistor and a fourth transistor series-connected to said third transistor, in which input terminals of said third and fourth transistors to which an output signal from said first inverter is inputted are commonly connected to each other, and output terminals of said third and fourth transistors are commonly connected to each other.
Claim 3
Dependent Claim 67 words
A ring oscillator type VCO (voltage-controlled oscillator) wherein: plural stages of inverter circuits are cascade-connected to each other, thereby constituting a positive feedback loop; at least one inverter circuit among said plural stages of inverter circuits comprises three stages of inverters constructed of load transistors and driver transistors; and a control voltage is applied to the load transistors of two adjoining inverters among said three-stages of inverters.
Claim 4
Dependent Claim 67 words
A ring oscillator type VCO (voltage-controlled oscillator) wherein: plural stages of inverter circuits are cascade-connected to each other, thereby constituting a positive feedback loop; at least one inverter circuit among said plural stages of inverter circuits comprises three stages of inverters constructed of load transistors and driver transistors; and a control voltage is applied to the load transistors of two adjoining inverters among said three-stages of inverters.
Claim 5
Dependent Claim 44 words
A ring oscillator type VCO as claimed in claim 2 wherein: each of said inverters includes a p-channel MOS transistor and an n-channel MOS transistor; and said p-channel MOS transistor is the load transistor having a gate to which the control voltage is applied.
Claim 6
Dependent Claim 44 words
A ring oscillator type VCO as claimed in claim 2, wherein: each of said inverters includes a p-channel MOS transistor and an n-channel MOS transistor: and said n-channel MOS transistor is the load transistor having a gate to which the control voltage is applied.
Claim 7
Dependent Claim 196 words
A ring oscillator type VCO circuit comprising: a voltage source; a source of reference potential; an even-numbered plurality of cascade-connected inverters comprising at least first and second stage inverters, each of said inverters including a series-connected circuit of a p-channel MOS transistor and an n-channel MOS transistor connected between said voltage source and said source of reference potential; a control voltage for each of one of said p-channel MOS transistors and said n-channel MOS transistors in said first and said second stage inverters which commonly function as load transistors, so that the other of said p-channel MOS transistors and said n-channel MOS transistors in said first and said second stage inverters commonly function as driver transistors; a voltage input provided to the driver transistor in said first inverter stage; a third inverter stage connected to the output of said even-numbered plurality of said inverters; a voltage output signal from said third inverter stage connected to said even-numbered plurality of said inverters, said voltage output signal having a rising edge and a falling edge delayed in a similar manner so that the duty ratio of the output signal can be continuously maintained at about a constant value.
Claim 8
Dependent Claim 196 words
A ring oscillator type VCO circuit comprising: a voltage source; a source of reference potential; an even-numbered plurality of cascade-connected inverters comprising at least first and second stage inverters, each of said inverters including a series-connected circuit of a p-channel MOS transistor and an n-channel MOS transistor connected between said voltage source and said source of reference potential; a control voltage for each of one of said p-channel MOS transistors and said n-channel MOS transistors in said first and said second stage inverters which commonly function as load transistors, so that the other of said p-channel MOS transistors and said n-channel MOS transistors in said first and said second stage inverters commonly function as driver transistors; a voltage input provided to the driver transistor in said first inverter stage; a third inverter stage connected to the output of said even-numbered plurality of said inverters; a voltage output signal from said third inverter stage connected to said even-numbered plurality of said inverters, said voltage output signal having a rising edge and a falling edge delayed in a similar manner so that the duty ratio of the output signal can be continuously maintained at about a constant value.
Claim 9
Dependent Claim 25 words
A ring oscillator type VCO circuit as set forth in claim 5 wherein said even-numbered, cascade-connected plurality of inverter circuits include a positive feedback loop.
Claim 10
Dependent Claim 39 words
A ring oscillator type VCO circuit as set forth in claim 5 wherein the p-channel MOS transistors of the first and second stage inverters are employed as load transistors and the n-channel MOS transistors are employed as driver transistors.
Claim 11
Dependent Claim 28 words
A ring oscillator type VCO circuit as set forth in claim 7 wherein each of said load transistors includes a gate to which said control voltage is provided.
Claim 12
Dependent Claim 29 words
A ring oscillator type VCO circuit as set forth in claim 5 further including a load capacitance connected at an output of said even-numbered plurality of said cascade-connected inverters.

References Cited (Backward Citations)

JPH0253304A Cited
EP0416145A1 Cited
US5038118A Cited
US5081428A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-10-09 1999-04-10 1999-10-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-10-09 2003-04-10 2003-10-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-10-09 2007-04-10 2007-10-10 $7700.00 Window Closed / Lapsed

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