Inverter circuit and level shifter circuit for providing a high voltage output

Claim 2

A transistorized inverter circuit comprising: an input terminal; an output terminal; a first field effect transistor of a first conductivity type connected between a first power source line and said output terminal and having a gate electrode connected to said input terminal; second to (n+1)th field effect transistors of a second conductivity type connected in series between said output terminal and a reference voltage line and having gate electrodes respectively connected to said input terminal; and voltage supply means for supplying (n-1) in number of second to (n)th power source voltages, whose absolute values become smaller in order, to respective junction of series connected second to (n+1)th transistors when the second to (n+1) th transistors are in OFF state.

Claim 3

The circuit as set forth in claim 1, where in said voltage supply means comprises (n-1) in number of field effect transistors of the first conductive type respectively supply corresponding power source voltages for respective of (n-1) in number of junctions of series connected (n-1) in number of second to (n+1)th transistors.

Claim 4

The circuit as set forth in claim 2, wherein said first and second conductivity types are P and N-channel, respectively.

Claim 5

A transistorized inverter circuit comprising: an input terminal; an output terminal; a first field effect transistor of a first conductivity type connected between a first power source line and said output terminal and having a gate electrode connected to said input terminal; second and third field effect transistors of a second conductivity type mutually connected in series between said output terminal and a reference voltage line and having respective gate electrodes connected to said input terminal; and a fourth field effect transistor of the first conductivity type connected between a second power source line having smaller absolute value of a power source voltage than that of said first power source line and a junction of the series connected second and third field effect transistors, and having a gate electrode connected to said input terminal.

Claim 6

A transistorized inverter circuit comprising: an input terminal; an output terminal; a first field effect transistor of a first conductivity type connected between a first power source line and said output terminal and having a gate electrode connected to said input terminal; second and third field effect transistors of a second conductivity type mutually connected in series between said output terminal and a reference voltage line and having respective gate electrodes connected to said input terminal; and a fourth field effect transistor of the first conductivity type connected between a second power source line having smaller absolute value of a power source voltage than that of said first power source line and a junction of the series connected second and third field effect transistors, and having a gate electrode connected to said input terminal.

Claim 7

The circuit as set forth in claim 4, wherein said first conductivity type is P-channel type and said second conductivity type is N-channel type.

Claim 8

The circuit as set forth in claim 5, wherein said power source voltage of said second power source line is substantially half said power source voltage of said first power source line.

Claim 9

A transistorized inverter circuit comprising: an input terminal; an output terminal; a first field effect transistor of a first conductivity type connected between a first power source line and a first node and having a gate electrode connected to said input terminal; second and third field effect transistors of a second conductivity type mutually connected in series between said first node and a reference voltage line and having respective gate electrodes connected to said input terminal; a fourth field effect transistor of the first conductivity type connected between a second power source line having smaller absolute value of a power source voltage than that of said first power source line and a junction of the series connected second and third field effect transistors, and having a gate electrode connected to said input terminal; a fifth field effect transistor of said first conductivity type connected between said first power source line and said output terminal and having a gate electrode connected to said first node; sixth and seventh field effect transistors of said second conductivity type connected in series between said output terminal and said reference voltage line, and respectively having gate electrodes, to which an inverted signal of an input signal is applied; and an eighth field effect transistor of said first conductivity type connected between said second power source line and a junction between series connected sixth and seventh field effect transistors and having a gate electrode connected to receive said inverted signal.

Claim 10

A transistorized inverter circuit comprising: an input terminal; an output terminal; a first field effect transistor of a first conductivity type connected between a first power source line and a first node and having a gate electrode connected to said input terminal; second and third field effect transistors of a second conductivity type mutually connected in series between said first node and a reference voltage line and having respective gate electrodes connected to said input terminal; a fourth field effect transistor of the first conductivity type connected between a second power source line having smaller absolute value of a power source voltage than that of said first power source line and a junction of the series connected second and third field effect transistors, and having a gate electrode connected to said input terminal; a fifth field effect transistor of said first conductivity type connected between said first power source line and said output terminal and having a gate electrode connected to said first node; sixth and seventh field effect transistors of said second conductivity type connected in series between said output terminal and said reference voltage line, and respectively having gate electrodes, to which an inverted signal of an input signal is applied; and an eighth field effect transistor of said first conductivity type connected between said second power source line and a junction between series connected sixth and seventh field effect transistors and having a gate electrode connected to receive said inverted signal.

Claim 11

The circuit as set forth in claim 7, wherein said input signal has two voltage levels, one of which is a level having smaller absolute value than a voltage level of said first power source line and a voltage level of said reference voltage line; and an output signal of said output terminal has two levels of a voltage level of said first power source line and a voltage level of said reference voltage line.

Claim 12

The circuit as set forth in claim 7, which further comprises an inverter circuit generating said inverted signal of said input signal.

Claim 13

The circuit as set forth in claim 8, wherein said inverted signal is extracted from a junction between the series connected second and third field effect transistors.

Claim 14

The circuit as set forth in claim 7, wherein said first conductivity type is P-channel type and said second conductivity type is N-channel type.

Claim 15

The circuit as set forth in claim 11, wherein said power source voltage of said second power source line is substantially half a power source voltage of said first power source line.