US5457405A
Expired / Lapsed
US
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Complementary logic recovered energy circuit
Assignee: Motorola Solutions Inc
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Filing: 1994-12-27
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Granted: 1995-10-10
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Expires: 2014-12-27
Abstract
Abstract A circuit derives all power from a single clock input terminal and has no connections to separate power source or power sink terminals. The circuit configuration is applicable to many functions such as inverters, logic gates (NAND, NOR, etc.), and storage elements. When connected to form an inverter function, a current electrode of a first transistor is coupled to the clock input terminal and a control electrode is coupled to a signal input terminal while a second transistor has a current electrode coupled to the clock input terminal and a control electrode coupled the signal input terminal. Both transistors have a second current electrode coupled to an output of the inverter.
Inventors
- 👤 William J. Ooms
- 👤 Jerald A. Hallmark
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:51
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K19/0019; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
138 words
A complementary logic recovered energy circuit comprising: a clock input terminal; a first signal input terminal; an output terminal; a first transistor of a first conductivity type having a first current electrode coupled to the output terminal, a second current electrode, and a control electrode coupled to the first signal input terminal; a second transistor of a second conductivity type having a first current electrode coupled to the clock input terminal, a second current electrode coupled to the output, and a control electrode coupled to the first signal input terminal; and a third transistor of the first conductivity type having a first current electrode coupled to the clock input terminal, a second current electrode coupled to the second current electrode of the first transistor, and a control electrode coupled to a second signal input terminal of the circuit.
Claim 2
Dependent Claim
138 words
A complementary logic recovered energy circuit comprising: a clock input terminal; a first signal input terminal; an output terminal; a first transistor of a first conductivity type having a first current electrode coupled to the output terminal, a second current electrode, and a control electrode coupled to the first signal input terminal; a second transistor of a second conductivity type having a first current electrode coupled to the clock input terminal, a second current electrode coupled to the output, and a control electrode coupled to the first signal input terminal; and a third transistor of the first conductivity type having a first current electrode coupled to the clock input terminal, a second current electrode coupled to the second current electrode of the first transistor, and a control electrode coupled to a second signal input terminal of the circuit.
Claim 3
Dependent Claim
45 words
The circuit of claim 1 further including a fourth transistor of the second conductivity type having a first current electrode coupled to the clock input terminal, a second current electrode coupled to the output, and a control electrode coupled to the second signal input terminal.
Claim 4
Independent Claim
74 words
A method of forming a complementary logic circuit comprising: coupling a clock terminal as both a power source terminal and a power sink terminal of the complementary logic circuit wherein a complete clock cycle is required to transfer a logic state from an input to an output of the circuit; and changing an output voltage of the complementary logic circuit but not an input voltage of the complementary logic circuit during a clock cycle.
Claim 5
Independent Claim
74 words
A method of forming a complementary logic circuit comprising: coupling a clock terminal as both a power source terminal and a power sink terminal of the complementary logic circuit wherein a complete clock cycle is required to transfer a logic state from an input to an output of the circuit; and changing an output voltage of the complementary logic circuit but not an input voltage of the complementary logic circuit during a clock cycle.
References Cited (Backward Citations)
US5378940A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-09 | 1999-04-10 | 1999-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-09 | 2003-04-10 | 2003-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-09 | 2007-04-10 | 2007-10-10 | $7700.00 | Window Closed / Lapsed |