US5452253A
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Burn-in test circuit for semiconductor memory device
Assignee: SK Hynix Inc
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Filing: 1993-09-23
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Granted: 1995-09-19
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Expires: 2013-09-23
Abstract
Abstract For enabling burn-in test in a memory device such that a test mode timing signal and detected voltage level of an external power supply are combined in order to maintain compatibility with conventional timing signals, and for preventing the burn-in test circuit from dissipating power in a standby state, there is provided a sense control circuit for producing a short duration enable pulse in response to an input level of timing signals such as WCBR, CBR, or ROR, and a voltage sensor for sensing the input voltage level of the external power supply voltage during the short duration pulse. Also, the circuit includes a burn-in sensor which generates a signal output which determines set or reset of the burn-in test mode in response to the timing signals and the detected level of the voltage sensor. Since the voltage sensor is operated only when the short duration pulse is applied, the power consumption in the voltage sensor is negligible even during the sensing operation of the external supply voltage. Further, the burn-in test mode is activated in the memory device if the external input signals satisfy the particular condition and the level of the external supply voltage is higher than the preset burn-in test voltage, thereby the memory device is prevented from entering into the burn-in test mode due to noise of the external power supply voltage.
Inventors
- 👤 Young-Keun Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:33
CPC Classifications
H; H10; H10P; H10P74/00; G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46; G11C29/50
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
182 words
A burn-in test circuit for a semiconductor memory device comprising: a reference voltage generator for generating a reference voltage; a timing generator for generating timing signals responsive to external input signals; a sense control circuit for producing a short duration pulse in response to the timing signals; a voltage sensor for sensing the input voltage level of an external power supply voltage, and for generating an output signal responsive to whether the input voltage level of the external power supply voltage is higher than a preset voltage level during the time when the short duration pulse is supplied from the sense control circuit; a burn-in sensor for generating an output signal which determines start or stop of a burn-in test mode on the basis of the timing signals and the output signal of the voltage sensor; and an internal voltage generator for supplying a constant internal voltage based on the reference voltage or an increasing internal voltage derived from the external power supply voltage to a memory array of the memory device in response to the output signal of the burn-in sensor.
Claim 2
Dependent Claim
182 words
A burn-in test circuit for a semiconductor memory device comprising: a reference voltage generator for generating a reference voltage; a timing generator for generating timing signals responsive to external input signals; a sense control circuit for producing a short duration pulse in response to the timing signals; a voltage sensor for sensing the input voltage level of an external power supply voltage, and for generating an output signal responsive to whether the input voltage level of the external power supply voltage is higher than a preset voltage level during the time when the short duration pulse is supplied from the sense control circuit; a burn-in sensor for generating an output signal which determines start or stop of a burn-in test mode on the basis of the timing signals and the output signal of the voltage sensor; and an internal voltage generator for supplying a constant internal voltage based on the reference voltage or an increasing internal voltage derived from the external power supply voltage to a memory array of the memory device in response to the output signal of the burn-in sensor.
Claim 3
Dependent Claim
104 words
A burn-in test circuit according to claim 1, wherein the external signals include a column address strobe signal, a row address strobe signal and a write enable signal each having an active and inactive state, wherein the burn-in sensor generates the output signal which determines start of the burn-in test mode if the column address strobe signal and the write enable signal are in the active state when the row address strobe signal changes its state from inactive to active at a time when the voltage level of the external power supply detected by the voltage sensor is higher than the preset voltage level.
Claim 4
Dependent Claim
133 words
A burn-in test circuit according to claim 1, wherein the external signals include a column address strobe signal, a row address strobe signal and a write enable signal each having an active and inactive state, wherein the burn-in sensor generates the output signal which determines stop of the burn-in test mode if the column address strobe signal is in the active state and the write enable signal is in the inactive state when the row address strobe signal changes its state from inactive to active, or if the column address strobe signal maintains an inactive state when the row address strobe signal changes its state from inactive to active and again to inactive, at a time when the detected voltage level of the external power supply is lower than the preset voltage level.
Claim 5
Dependent Claim
80 words
A burn-in test circuit according to claim 1, wherein the sense control circuit comprises a NOR gate for receiving timing signals from the timing generator, a first inverter connected to the output of the NOR gate, an even numbered chain of inverters parallelly coupled to the first inverter, a NAND gate with inputs connected to the outputs of the first inverter and the last of the chain of inverters, and second inverter connected to the output of the NAND gate.
Claim 6
Dependent Claim
220 words
A burn-in test circuit according to claim 1, wherein the burn-in sensor comprises a first NAND gate receiving as inputs a first timing signal generated by the timing generator and the output signal generated by the voltage sensor, a first NOR gate receiving as inputs second and third timing signals generated by the timing generator, a second NOR gate receiving as an input the output of the first NAND gate and receiving as another input a reset signal coupled to a reset input terminal through a second inverter, a Flip-Flop having set and reset inputs and an output, wherein the output of the second NOR gate is coupled to the set input of the Flip-Flop, a second NAND gate receiving as an input the output of the first NOR gate through a second inverter and as another input thereof the output signal generated by the voltage sensor through a third inverter, wherein the output of the second NAND gate is connected to one input of a third NAND gate G14 and a second input of the third NAND gate is coupled to receive the reset signal, wherein the output of the third NAND gate is coupled to a reset input of the Flip-Flop, and wherein at the output of the Flip-Flop the output signal of the burn-in sensor is generated.
Claim 7
Dependent Claim
169 words
A test mode control circuit for a semiconductor device such as a memory device operative in a normal mode and a burn-in test mode, comprising: a timing generator for generating one or more timing signals in response to one or more external input signals to the semiconductor device; a sense control circuit for producing a short duration pulse signal in response to one or more of the timing signals generated by the timing generator; a voltage sensor for sensing a voltage level supplied to the semiconductor device by an external power supply, wherein the voltage sensor generates a first output signal if the sensed voltage level exceeds a predetermined voltage level only during the short duration pulse signal generated by the sense control circuit; a burn-in sensor for generating a burn-in mode test signal responsive to one or more of the timing signals and the first output signal of the voltage sensor, wherein the semiconductor device operates in the burn-in test mode responsive to the burn-in mode test signal.
Claim 8
Dependent Claim
169 words
A test mode control circuit for a semiconductor device such as a memory device operative in a normal mode and a burn-in test mode, comprising: a timing generator for generating one or more timing signals in response to one or more external input signals to the semiconductor device; a sense control circuit for producing a short duration pulse signal in response to one or more of the timing signals generated by the timing generator; a voltage sensor for sensing a voltage level supplied to the semiconductor device by an external power supply, wherein the voltage sensor generates a first output signal if the sensed voltage level exceeds a predetermined voltage level only during the short duration pulse signal generated by the sense control circuit; a burn-in sensor for generating a burn-in mode test signal responsive to one or more of the timing signals and the first output signal of the voltage sensor, wherein the semiconductor device operates in the burn-in test mode responsive to the burn-in mode test signal.
Claim 9
Dependent Claim
77 words
The apparatus of claim 6, wherein the voltage sensor generates a second output signal if the sensed voltage level does not exceed the predetermined voltage level during the short duration pulse signal generated by the sense control circuit, wherein the burn-in sensor does not generate a burn-in mode test signal responsive to one or more of the timing signals and the second output signal of the voltage sensor, wherein the semiconductor device operates in the normal mode.
Claim 10
Dependent Claim
93 words
The apparatus of claim 6, wherein the external signals include a column address strobe signal, a row address strobe signal and a write enable signal each having an active and inactive state, wherein the burn-in sensor generates the burn-in test mode signal if the column address strobe signal and the write enable signal are in the active state when the row address strobe signal changes its state from inactive to active at a time when the voltage level of the external power supply detected by the voltage sensor exceeds the predetermined voltage level.
Claim 11
Dependent Claim
123 words
The apparatus of claim 7, wherein the external signals include a column address strobe signal, a row address strobe signal and a write enable signal each having an active and inactive state, wherein the burn-in sensor generates a normal mode signal if the column address strobe signal is in the active state and the write enable signal is in the inactive state when the row address strobe signal changes its state from inactive to active, or if the column address strobe signal maintains an inactive state when the row address strobe signal changes its state from inactive to active and again to inactive, at a time when the detected voltage level of the external power supply does not exceed the predetermined voltage level.
Claim 12
Dependent Claim
111 words
The apparatus of claim 8, wherein the burn-in sensor generates a normal mode signal if the column address strobe signal is in the active state and the write enable signal is in the inactive state when the row address strobe signal changes its state from inactive to active, or if the column address strobe signal maintains an inactive state when the row address strobe signal changes its state from inactive to active and again to inactive, at a time when the detected voltage level of the external power supply does not exceed the predetermined voltage level, wherein the semiconductor device operates in the normal mode responsive to the normal mode signal.
Claim 13
Dependent Claim
112 words
In a semiconductor device such as a memory device, a method for activating a burn-in test mode of the semiconductor device comprising: generating one or more timing signals responsive to one or more external input signals to the semiconductor device; generating a short duration pulse signal responsive to one or more of the timing signals; sensing an input voltage supplied to the semiconductor device and generating a first signal if the sensed input voltage exceeds a predetermined threshold voltage only during the short duration pulse signal; generating a burn-in test mode signal responsive to the first signal, wherein the burn-in test mode signal activates the burn-in test mode of the semiconductor device.
Claim 14
Dependent Claim
112 words
In a semiconductor device such as a memory device, a method for activating a burn-in test mode of the semiconductor device comprising: generating one or more timing signals responsive to one or more external input signals to the semiconductor device; generating a short duration pulse signal responsive to one or more of the timing signals; sensing an input voltage supplied to the semiconductor device and generating a first signal if the sensed input voltage exceeds a predetermined threshold voltage only during the short duration pulse signal; generating a burn-in test mode signal responsive to the first signal, wherein the burn-in test mode signal activates the burn-in test mode of the semiconductor device.
Claim 15
Dependent Claim
43 words
The method of claim 11, wherein a second signal is generated if the sensed input voltage does not exceed a predetermined threshold voltage during the short duration pulse signal, wherein the semiconductor device operates in a normal mode responsive to the second signal.
Claim 16
Dependent Claim
85 words
The method of claim 11, wherein the external signals include a column address strobe signal, a row address strobe signal and a write enable signal each having an active and inactive state, wherein the burn-in test mode signal is generated if the column address strobe signal and the write enable signal are in the active state when the row address strobe signal changes its state from inactive to active at a time when the voltage level of the input voltage exceeds the predetermined voltage level.
Claim 17
Dependent Claim
134 words
The method of claim 12, wherein the external signals include a column address strobe signal, a row address strobe signal and a write enable signal each having an active and inactive state, wherein a normal mode signal is generated if the column address strobe signal is in the active state and the write enable signal is in the inactive state when the row address strobe signal changes its state from inactive to active, or if the column address strobe signal maintains an inactive state when the row address strobe signal changes its state from inactive to active and again to inactive, at a time when the voltage level of the input voltage does not exceed the predetermined voltage level, wherein the semiconductor device operates in the normal mode responsive to the normal mode signal.
Claim 18
Dependent Claim
107 words
The method of claim 13, wherein a normal mode signal is generated if the column address strobe signal is in the active state and the write enable signal is in the inactive state when the row address strobe signal changes its state from inactive to active, or if the column address strobe signal maintains an inactive state when the row address strobe signal changes its state from inactive to active and again to inactive, at a time when the voltage level of the input voltage does not exceed the predetermined voltage level, wherein the semiconductor device operates in a normal mode responsive to the normal mode signal.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |