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US5452016A
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Combined digital color control and chroma killer device
Assignee: Texas Instruments Japan Ltd
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Filing: 1993-03-10
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Granted: 1995-09-19
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Expires: 2013-03-10
Abstract
Abstract An automatic color control and chroma killer circuit 3 and video processing system is provided that is capable of controlling an amplitude of a color signal and of performing a killer function with a simple construction without using a divider and/or vertical filter. The ACC/ACK device includes ACC and ACK circuitry which may be selectively enabled with operating signals to a selector 27. When the selector 27 enables amplitude detector 25, the amplitude detector 25 detects amplitude of the input color signal and a coefficient controller 26 compares it with a killer level. If the input color signal fails to meet the killer level then the coefficient controller 26 controls a coefficient generated by the coefficient generator 22 to perform a killer operation. The ACC operation and circuitry is thereby ACK controlled until an input color signal meets or exceeds the killer level. When the selector 27 enables the multiplier circuit 11 according to an operating signal input, the input color signal is ACC controlled by the multiplier circuit 11, and amplitude detector 21, a coefficient generator 22, a coefficient memory 23 and a delay circuit 24.
Inventors
- 👤 Kazuhiro Ohara
- 👤 Masafumi Yugami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 10:27
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/70; H04N9/71
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
116 words
A digital automatic color control and chroma killer (ACC/ACK) device, comprising: ACK circuitry for killing color signals failing to meet a minimum: signal value and ACC circuitry for modifying amplitudes of said color signals responsive to said ACK circuitry or according to determined relationships between said color signals and a reference color signal and said ACC circuitry includes circuitry for developing an output color signal according to the recursive formula c.sub.n+1 =s.sub.n+1 ·k.sub.n (s.sub.n), where c is the output color signal, s is the input color signal, k is an operator developed from said determined relationships, and n and n`represent successive time periods; and wherein said ACK and ACC circuitry do not contain a divider circuit.
Claim 2
Dependent Claim
116 words
A digital automatic color control and chroma killer (ACC/ACK) device, comprising: ACK circuitry for killing color signals failing to meet a minimum: signal value and ACC circuitry for modifying amplitudes of said color signals responsive to said ACK circuitry or according to determined relationships between said color signals and a reference color signal and said ACC circuitry includes circuitry for developing an output color signal according to the recursive formula c.sub.n+1 =s.sub.n+1 ·k.sub.n (s.sub.n), where c is the output color signal, s is the input color signal, k is an operator developed from said determined relationships, and n and n`represent successive time periods; and wherein said ACK and ACC circuitry do not contain a divider circuit.
Claim 3
Dependent Claim
57 words
The ACC/ACK device of claim 1, wherein said ACK circuitry includes: a detector for detecting amplitudes of said color signals; and, control circuitry for testing a portion of said color signals against said minimum signal value and for controlling modification of said amplitudes by said ACC circuitry where said portion fails to meet said minimum signal value.
Claim 4
Dependent Claim
57 words
The ACC/ACK device of claim 1, said ACC circuitry including: a detector for detecting amplitudes of said color signals; coefficient circuitry for determining relationships between said color signals and said reference color signal and for developing operators according to said relationships subject to said ACK circuit; and, a multiplier for multiplying said operators with said color signals.
Claim 5
Dependent Claim
23 words
The ACC/ACK device of claim 3, wherein said ACC circuitry includes delay circuitry for synchronizing multiplying of said operators with said color signals.
Claim 6
Dependent Claim
31 words
The ACC/ACK device of claim 1, further comprising: an input for receiving said color signals; and, a selector for selectively connecting said ACK circuitry or said ACC circuitry to said input.
Claim 7
Dependent Claim
192 words
A digital ACC/ACK circuit comprising: (a) a multiplier for multiplying an input digital color signal with a first coefficient and outputting a color signal; (b) an amplitude detector for detecting an amplitude value of the color signal output from said multiplier; (c) a coefficient generator for generating the first coefficient based on the amplitude value of the color signal and a second coefficient; (d) a delay means for delaying a signal comprising the first coefficient output from said coefficient generator and supplying the delay signal to said multiplier; (e) a coefficient memory means for updating the second coefficient to the first coefficient and storing the latter; (f) a coefficient controller including a comparator circuit for comparing the amplitude value of the input digital color signal with a killer level value and outputting a discrimination value, a memory device for storing the discrimination value output from said comparator circuit and a control circuit for controlling the first coefficient generated by said coefficient generator according to the discrimination value stored in said memory device; and (g) a selector for selectively supplying the input digital color signal to said multiplier circuit and said coefficient controller.
Claim 8
Dependent Claim
192 words
A digital ACC/ACK circuit comprising: (a) a multiplier for multiplying an input digital color signal with a first coefficient and outputting a color signal; (b) an amplitude detector for detecting an amplitude value of the color signal output from said multiplier; (c) a coefficient generator for generating the first coefficient based on the amplitude value of the color signal and a second coefficient; (d) a delay means for delaying a signal comprising the first coefficient output from said coefficient generator and supplying the delay signal to said multiplier; (e) a coefficient memory means for updating the second coefficient to the first coefficient and storing the latter; (f) a coefficient controller including a comparator circuit for comparing the amplitude value of the input digital color signal with a killer level value and outputting a discrimination value, a memory device for storing the discrimination value output from said comparator circuit and a control circuit for controlling the first coefficient generated by said coefficient generator according to the discrimination value stored in said memory device; and (g) a selector for selectively supplying the input digital color signal to said multiplier circuit and said coefficient controller.
Claim 9
Dependent Claim
212 words
A digital ACC/ACK circuit comprising: (a) a multiplier for multiplying an input digital color signal with a first coefficient and outputting a color signal; (b) a first amplitude detector for detecting an amplitude value of the color signal output from said multiplier; (c) a coefficient generator for generating the first coefficient based on the amplitude value of the color signal and a second coefficient; (d) a delay means for delaying a signal comprising of the first coefficient output from said coefficient generator and supplying the delay signal to said multiplier circuit; (e) a coefficient memory means for updating the second coefficient to the first coefficient and storing the latter; (f) a second amplitude detector for detecting an amplitude value of the input digital color signal; (g) a coefficient controller including a comparator circuit for comparing the amplitude value of the input digital color signal with a killer level value and outputting a discrimination value, a memory device for storing the discrimination value output from said comparator circuit and a control circuit for controlling the first coefficient generated by said coefficient generator according to the discrimination value stored in said memory device; and (h) a selector for selectively supplying the input digital color signal to said multiplier circuit or said second amplitude detector.
Claim 10
Dependent Claim
212 words
A digital ACC/ACK circuit comprising: (a) a multiplier for multiplying an input digital color signal with a first coefficient and outputting a color signal; (b) a first amplitude detector for detecting an amplitude value of the color signal output from said multiplier; (c) a coefficient generator for generating the first coefficient based on the amplitude value of the color signal and a second coefficient; (d) a delay means for delaying a signal comprising of the first coefficient output from said coefficient generator and supplying the delay signal to said multiplier circuit; (e) a coefficient memory means for updating the second coefficient to the first coefficient and storing the latter; (f) a second amplitude detector for detecting an amplitude value of the input digital color signal; (g) a coefficient controller including a comparator circuit for comparing the amplitude value of the input digital color signal with a killer level value and outputting a discrimination value, a memory device for storing the discrimination value output from said comparator circuit and a control circuit for controlling the first coefficient generated by said coefficient generator according to the discrimination value stored in said memory device; and (h) a selector for selectively supplying the input digital color signal to said multiplier circuit or said second amplitude detector.
Claim 11
Dependent Claim
102 words
The digital ACC/ACK circuit as in claim 7, wherein said amplitude detector comprising: a burst data selector for selecting and outputting a portion of the burst signal; an absolute value circuit for obtaining an absolute value of an output of said burst data selector; a square sum circuit for obtaining and outputting a square sum of the output of said absolute value circuit; a square root circuit for obtaining a square root of the output of said square sum circuit; and a horizontal sum and average circuit for obtaining and outputting a horizontally summed and averaged output of said square root circuit.
Claim 12
Dependent Claim
108 words
The digital ACC/ACK circuit as in claim 7, said coefficient generator comprising: a discrimination signal generator for comparing the amplitude value of the color signal output from said multiplier with a reference amplitude value to generate a discrimination signal indicative of at least three states where the color signal is smaller than, equal to and larger than the reference amplitude; an adder/subtracter circuit for generating said first coefficient by adding the discrimination signal to or subtracting the discrimination signal from said second coefficient; and a limiter circuit for limiting the output of said adder/subtracter circuit so that it does not exceed a bit width of said coefficient memory.
Claim 13
Dependent Claim
180 words
A digital chroma killer circuit comprising: (a) a multiplier circuit for multiplying an input digital color signal with a predetermined coefficient and outputting a color signal; (b) an amplitude detector for detecting an amplitude value of the input digital color signal; (c) a coefficient controller including a comparator circuit for comparing the amplitude value of the input digital color signal with a killer level value and outputting a discrimination value, a memory device for storing said discrimination value output from said comparator circuit and a control circuit for performing a chroma killer operation by controlling said predetermined coefficient according to the discrimination value stored in said memory device; (d) a coefficient generator for generating said predetermined coefficient; (e) a coefficient memory for storing said predetermined coefficient generated by said coefficient generator; (f) a delay means for delaying a signal corresponding to the value of said predetermined coefficient output from said coefficient generator and supplying said signal to said multiplier circuit; and, (g) a selector for selectively supplying the input digital color signal to said multiplier circuit and said amplitude detector.
Claim 14
Dependent Claim
180 words
A digital chroma killer circuit comprising: (a) a multiplier circuit for multiplying an input digital color signal with a predetermined coefficient and outputting a color signal; (b) an amplitude detector for detecting an amplitude value of the input digital color signal; (c) a coefficient controller including a comparator circuit for comparing the amplitude value of the input digital color signal with a killer level value and outputting a discrimination value, a memory device for storing said discrimination value output from said comparator circuit and a control circuit for performing a chroma killer operation by controlling said predetermined coefficient according to the discrimination value stored in said memory device; (d) a coefficient generator for generating said predetermined coefficient; (e) a coefficient memory for storing said predetermined coefficient generated by said coefficient generator; (f) a delay means for delaying a signal corresponding to the value of said predetermined coefficient output from said coefficient generator and supplying said signal to said multiplier circuit; and, (g) a selector for selectively supplying the input digital color signal to said multiplier circuit and said amplitude detector.
Claim 15
Dependent Claim
25 words
The digital chroma killer circuit as in claim 10, said memory device including means for updating memory only when said selector selects said amplitude detector.
Claim 16
Dependent Claim
35 words
The digital chroma killer circuit as in claim 10, said selector including means for selecting either said multiplier circuit or said amplitude detector within respective fields of a television signal in a time sharing manner.
Claim 17
Dependent Claim
170 words
A digital automatic color control and chroma killer circuit comprising a first selector including an input terminal, and selectable output terminals A and B; a first amplitude detector connected to said output terminal A; a coefficient controller connected to said first amplitude detector; a second selector including selectable input terminals C and D and an output terminal; said input terminal C connected to said output terminal A; a multiplier including operand and operator input ports and resultant output port; said multiplicand port connected to said output terminal B; said resultant port connected to said input terminal D; a second amplitude detector connected to said resultant port; a coefficient generator connected to said second amplitude detector and said coefficient controller; a coefficient memory connected to said coefficient generator; a switch including input terminal E and output terminal F; said input terminal E connected to said coefficient generator; and, a delay circuit connected to said operator input port; said first and second selectors and switch being controllable with externally propagated operating signals.
Claim 18
Dependent Claim
170 words
A digital automatic color control and chroma killer circuit comprising a first selector including an input terminal, and selectable output terminals A and B; a first amplitude detector connected to said output terminal A; a coefficient controller connected to said first amplitude detector; a second selector including selectable input terminals C and D and an output terminal; said input terminal C connected to said output terminal A; a multiplier including operand and operator input ports and resultant output port; said multiplicand port connected to said output terminal B; said resultant port connected to said input terminal D; a second amplitude detector connected to said resultant port; a coefficient generator connected to said second amplitude detector and said coefficient controller; a coefficient memory connected to said coefficient generator; a switch including input terminal E and output terminal F; said input terminal E connected to said coefficient generator; and, a delay circuit connected to said operator input port; said first and second selectors and switch being controllable with externally propagated operating signals.
Claim 19
Independent Claim
114 words
A method for digital automatic color control and chroma killing of color signals, comprising: a) killing any of said color signals failing to meet a minimum burst signal value; and, b) modifying amplitudes of said color signals according to step (a) or normalizing amplitudes of said color signals with operators derived by determining relationships between said color signals and a reference color signal without using a dividing algorithm and wherein an output color signal is developed according to the recursive formula c.sub.n+1 =s.sub.n+1 ·K.sub.n (s.sub.n), where c is an output color signal, s is an input color signal, k is an operator developed from said relationships, and n and n+1 represent successive time periods.
Claim 20
Independent Claim
114 words
A method for digital automatic color control and chroma killing of color signals, comprising: a) killing any of said color signals failing to meet a minimum burst signal value; and, b) modifying amplitudes of said color signals according to step (a) or normalizing amplitudes of said color signals with operators derived by determining relationships between said color signals and a reference color signal without using a dividing algorithm and wherein an output color signal is developed according to the recursive formula c.sub.n+1 =s.sub.n+1 ·K.sub.n (s.sub.n), where c is an output color signal, s is an input color signal, k is an operator developed from said relationships, and n and n+1 represent successive time periods.
Claim 21
Dependent Claim
127 words
The method of claim 14, further including: updating `k` with said coefficient generator according to the formula k.sub.n =k.sub.n-1 +d· where k n-l is an operator developed from comparison of s n-1 , or if n equals zero, then k n-1 is an initial predetermined value, `d` is a discrimination value obtained from said coefficient controller and having the following values: a negative value if an nth burst signal fails to meet or exceed said minimum burst signal or if s n is less than said reference color signal, or, if said nth burst signal meets or exceeds said minimum burst signal, then a zero value if s n corresponds to said reference color signal, or a positive value if s n exceeds said reference color signal.
Claim 22
Dependent Claim
54 words
The method of claim 14 wherein step (a) includes: i) detecting amplitudes of said color signals; and, ii) testing a burst signal from said color signals against a minimum burst signal value; and, iii) when said burst signal fails to meet said minimum burst signal value, reducing amplitudes of said color signals to zero.
Claim 23
Dependent Claim
45 words
The method as in claim 14, step (b) including: i) detecting amplitudes of said color signals; ii) determining relationships between said color signals and said reference color signal; iii ) developing operators according to step (ii); and, iv) multiplying said operators onto said color signals.
Claim 24
Dependent Claim
50 words
The method as in claim 14, said method including: selectively executing or skipping step (a) according to a timing pattern for receiving said burst signals; retaining a result from the previous execution of step (a) to which step (b) continues to be responsive until a next execution of step (a).
Claim 25
Dependent Claim
119 words
A digital method for automatic color control and chroma killing, comprising: a) multiplying an input digital color signal with a first coefficient and outputting a color signal; b) detecting an amplitude of the color signal output from step (a); c) generating said first coefficient based on said amplitude and a second coefficient; d) delaying said first coefficient prior to step (a) and synchronizing said first coefficient with said input digital color signal; e) updating said second coefficient to said first coefficient and storing; f) comparing the amplitude value of the input digital color signal with a killer level and outputting a discrimination value; g) storing said discrimination value; and, h) generating said first coefficient according to said discrimination value.
Claim 26
Dependent Claim
119 words
A digital method for automatic color control and chroma killing, comprising: a) multiplying an input digital color signal with a first coefficient and outputting a color signal; b) detecting an amplitude of the color signal output from step (a); c) generating said first coefficient based on said amplitude and a second coefficient; d) delaying said first coefficient prior to step (a) and synchronizing said first coefficient with said input digital color signal; e) updating said second coefficient to said first coefficient and storing; f) comparing the amplitude value of the input digital color signal with a killer level and outputting a discrimination value; g) storing said discrimination value; and, h) generating said first coefficient according to said discrimination value.
Claim 27
Dependent Claim
162 words
A digital method for image or video processing, comprising: a) receiving a video or image signal; b) separating said video or image signal into chrominance and luminance signals; c) normalizing or killing said chrominance signal s; and d) developing color signals by combining signals resulting from step (c) with said luminance signals; and wherein said step (c) includes: i) killing any of said chrominance signals failing to meet a minimum burst signal value; and, ii) modifying amplitudes of said chrominance signals according to step (i) or normalizing amplitudes of said chrominance signals with operators derived by determining relationships between said chrominance signals and a reference color signal without using a dividing algorithm, and wherein said step (c) further includes, developing an output color signal according to the recursive formula c.sub.n+1 =s.sub.n+1 ·k.sub.n (s.sub.n) where c is an output color signal, s is an input color signal, k is an operator developed from said relationships, and n and n+1 represent successive time periods.
Claim 28
Dependent Claim
162 words
A digital method for image or video processing, comprising: a) receiving a video or image signal; b) separating said video or image signal into chrominance and luminance signals; c) normalizing or killing said chrominance signal s; and d) developing color signals by combining signals resulting from step (c) with said luminance signals; and wherein said step (c) includes: i) killing any of said chrominance signals failing to meet a minimum burst signal value; and, ii) modifying amplitudes of said chrominance signals according to step (i) or normalizing amplitudes of said chrominance signals with operators derived by determining relationships between said chrominance signals and a reference color signal without using a dividing algorithm, and wherein said step (c) further includes, developing an output color signal according to the recursive formula c.sub.n+1 =s.sub.n+1 ·k.sub.n (s.sub.n) where c is an output color signal, s is an input color signal, k is an operator developed from said relationships, and n and n+1 represent successive time periods.
Claim 29
Dependent Claim
93 words
The method as in claim 20, step (c)(i) including: aa) detecting amplitudes of said color signals; bb) testing a burst signal from said color signals against a minimum burst signal value; and, cc) where said burst signal fails to meet said minimum burst signal value, reducing amplitudes of said color signals to zero; step (c)(ii) including: aa) detecting amplitudes of said color signals; bb) determining relationships between said color signals and said reference color signal; cc) developing operators according to step (c) (ii) (bb); and, dd) multiplying said operators onto said color signals.
Claim 30
Dependent Claim
50 words
The method of claim 20, said method including: selectively executing or skipping step (c)(i) according to a timing pattern for receiving said burst signals; and, retaining a result from the previous execution of step (c)(i) to which step (c)(ii) continues to be responsive until a next execution of step (c)(i).
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |