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US5451797A
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Method of fabricating a silicon carbide vertical MOSFET and device
Assignee: Motorola Solutions Inc
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Filing: 1995-01-09
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Granted: 1995-09-19
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Expires: 2015-01-09
Abstract
Abstract A silicon carbide vertical MOSFET formed on a silicon carbide substrate with portions of epitaxial layers defining the various transistor electrodes, rather than defining the electrodes with implants and diffusion. An opening is formed in some of the epitaxial layers and a conductive layer is formed therein to electrically connect a drain contact on the rear of the substrate to the components on the front of the substrate.
Inventors
- 👤 Kenneth L. Davis
- 👤 Charles E. Weitzel
- 👤 Neal J. Mellen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 03:37
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D12/00; H10D12/01; H10D12/031; H10D30/01; H10D30/021; H10D30/028; H10D30/0291; H10D62/00; H10D62/80; H10D62/83; H10D62/832; H10D62/8325; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/252; H10D64/2527; H10D64/256; Y; Y10; Y10S; Y10S148/00; Y10S148/148
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
181 words
A vertical FET comprising: a silicon carbide substrate of a first conductivity type with a surface; a first epitaxial layer of the first conductivity type positioned on the surface of the substrate, the first epitaxial layer being relatively lightly doped compared to the substrate and including a surface; a second epitaxial layer of a second conductivity type positioned on the surface of the first epitaxial layer; an opening defined by the second epitaxial layer and extending from the surface of the second epitaxial layer at least into communication with the first epitaxial layer; a relatively thin layer of the first conductivity type positioned in overlying relationship on the second epitaxial layer and surfaces of the opening through the second epitaxial layer, the relatively thin layer having an opening therethrough defining a gate region at a position spaced from the opening defined by the second epitaxial layer; a gate contact positioned in overlying relationship to the gate region; and a source contact positioned on a defined source region spaced from the gate region opposite the opening defined by the second epitaxial layer.
Claim 2
Dependent Claim
181 words
A vertical FET comprising: a silicon carbide substrate of a first conductivity type with a surface; a first epitaxial layer of the first conductivity type positioned on the surface of the substrate, the first epitaxial layer being relatively lightly doped compared to the substrate and including a surface; a second epitaxial layer of a second conductivity type positioned on the surface of the first epitaxial layer; an opening defined by the second epitaxial layer and extending from the surface of the second epitaxial layer at least into communication with the first epitaxial layer; a relatively thin layer of the first conductivity type positioned in overlying relationship on the second epitaxial layer and surfaces of the opening through the second epitaxial layer, the relatively thin layer having an opening therethrough defining a gate region at a position spaced from the opening defined by the second epitaxial layer; a gate contact positioned in overlying relationship to the gate region; and a source contact positioned on a defined source region spaced from the gate region opposite the opening defined by the second epitaxial layer.
Claim 3
Dependent Claim
42 words
A vertical FET as claimed in claim 1 wherein the gate contact includes a layer of gate oxide positioned on the relatively thin layer and a conductive material positioned on the layer of gate oxide in overlying relationship to the gate region.
Claim 4
Dependent Claim
39 words
A vertical FET as claimed in claim 1 including in addition a drain contact positioned on a second surface of the substrate and electrically coupled to the relatively thin layer in the opening defined by the second epitaxial layer.
Claim 5
Dependent Claim
247 words
A silicon carbide vertical MOSFET comprising: a silicon carbide substrate of a first conductivity type with a surface; a first epitaxial layer of the first conductivity type positioned on the surface of the substrate, the epitaxial layer being relatively lightly doped compared to the substrate and including a surface; a second epitaxial layer of a second conductivity type positioned on the surface of the first epitaxial layer, the second epitaxial layer having a surface; a relatively thin layer of material of the first conductivity type positioned on the surface of the second epitaxial layer, the relatively-thin layer defining an opening therethrough which defines a gate region at a position spaced from the opening defined by the second epitaxial layer; an opening defined in the second epitaxial layer and extending from the surface of the second epitaxial layer at least into communication with the first epitaxial layer; a layer of gate oxide positioned on the relatively thin layer and on the defined gate region, the gate oxide having an opening therethrough which defines a source region; a layer of conductive material positioned in the opening defined in the second epitaxial layer and providing a substantially short circuit between the relatively thin layer and the first epitaxial layer; a gate contact positioned on the layer of gate oxide in overlying relationship to the gate region; and a source contact positioned on a defined source region spaced from the gate region opposite the opening defined by the second epitaxial layer.
Claim 6
Dependent Claim
247 words
A silicon carbide vertical MOSFET comprising: a silicon carbide substrate of a first conductivity type with a surface; a first epitaxial layer of the first conductivity type positioned on the surface of the substrate, the epitaxial layer being relatively lightly doped compared to the substrate and including a surface; a second epitaxial layer of a second conductivity type positioned on the surface of the first epitaxial layer, the second epitaxial layer having a surface; a relatively thin layer of material of the first conductivity type positioned on the surface of the second epitaxial layer, the relatively-thin layer defining an opening therethrough which defines a gate region at a position spaced from the opening defined by the second epitaxial layer; an opening defined in the second epitaxial layer and extending from the surface of the second epitaxial layer at least into communication with the first epitaxial layer; a layer of gate oxide positioned on the relatively thin layer and on the defined gate region, the gate oxide having an opening therethrough which defines a source region; a layer of conductive material positioned in the opening defined in the second epitaxial layer and providing a substantially short circuit between the relatively thin layer and the first epitaxial layer; a gate contact positioned on the layer of gate oxide in overlying relationship to the gate region; and a source contact positioned on a defined source region spaced from the gate region opposite the opening defined by the second epitaxial layer.
Claim 7
Dependent Claim
44 words
A silicon carbide vertical MOSFET as claimed in claim 4 wherein the relatively thin layer is doped sufficiently heavily to form a substantially short circuit between the relatively thin layer positioned on the surface of the second epitaxial layer and the first epitaxial layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |