Abstract A binary image processing apparatus is provided which is capable of clearly and stably performing binary encoding of an image signal having a level corresponding to the density of each inputted pixel even when the difference in density between characters and background is small. Such apparatus includes a first level discriminating device which has a first input terminal for receiving an image signal having a level corresponding to the density of a pixel of the image signal and a second input terminal for receiving a signal indicative of a discrimination level so as to discriminate the level of the image signal by the discrimination level into binary data. A differential device obtains a differential value of the image signal at the pixel and a second level discriminating device discriminates the level of the differential value by a predetermined discrimination level. In response to image signals in the vicinity of the pixel, a calculating device determines an average value of density levels in the vicinity of the pixel and a discrimination level changing device supplies the average value to the second input terminal of the first level discriminating device but retains the discrimination level inputted to the second input terminal of the first level discriminating device when the differential value exceeds and is not more than the predetermined discrimination level.
A binary image processing apparatus comprising: an image signal generating means for sequentially generating a first image signal indicative of density of a target pixel; an electrical image signal correcting circuit which outputs, in response to the first image signal from said image signal generating means, a second image signal obtained by subjecting the first image signal to correction for improving contrast of the first image signal and for outputting a further first image signal of pixels disposed adjacent to the target pixel; an error diffusing circuit responsive to the second image signal and the further first image signal from said electrical image signal correcting circuit and also responsive to further first binary data of the pixel disposed adjacent to the target pixel, for correcting the second image signal so as to further reduce the variation of the pixel disposed adjacent to the target pixel when the variation between the level of the second image signal exceeds a predetermined discrimination level and for then determining the level of the second image signal so as to output first binary data relating to the first image signal; and a data compressing circuit which compresses the first binary data from said error diffusing circuit so as to not only output second binary data of the first image signal but also supply the further first binary data to said error diffusing circuit.
Claim 2
Dependent Claim
228 words
A binary image processing apparatus comprising: an image signal generating means for sequentially generating a first image signal indicative of density of a target pixel; an electrical image signal correcting circuit which outputs, in response to the first image signal from said image signal generating means, a second image signal obtained by subjecting the first image signal to correction for improving contrast of the first image signal and for outputting a further first image signal of pixels disposed adjacent to the target pixel; an error diffusing circuit responsive to the second image signal and the further first image signal from said electrical image signal correcting circuit and also responsive to further first binary data of the pixel disposed adjacent to the target pixel, for correcting the second image signal so as to further reduce the variation of the pixel disposed adjacent to the target pixel when the variation between the level of the second image signal exceeds a predetermined discrimination level and for then determining the level of the second image signal so as to output first binary data relating to the first image signal; and a data compressing circuit which compresses the first binary data from said error diffusing circuit so as to not only output second binary data of the first image signal but also supply the further first binary data to said error diffusing circuit.
Claim 3
Dependent Claim
43 words
A binary image processing apparatus as claimed in claim 1, wherein said electrical image signal correcting circuit includes an MTF (modulation transfer function) correcting circuit responsive to said first image signal for producing said second image signal and said further first image signal.
Claim 4
Dependent Claim
26 words
A binary image processing apparatus as in claim,1 wherein said image signal generating means includes an analog to digital converter for generating said first image signal.
Claim 5
Dependent Claim
72 words
A binary image processing apparatus as in claim 1 wherein said image signal generating means includes mean for sequentially scanning a document on a line-by-line basis and for sequentially generating a plurality of said first image signals, and said data compression circuit includes line buffer and switching means for compressing said first binary data corresponding to two lines of said first image signals into one scanning line of said second binary data.
Claim 6
Dependent Claim
69 words
A binary image processing apparatus as in claim 1 wherein said error diffusing circuit further includes error calculating circuits responsive to said further first image signal and said further first binary data for calculating error data of the pixels adjacent to said target pixel for use in correcting said second image signal, whereby said second binary data is produced without requiring a buffer memory for storing said error data.