US5448528A
Expired / Lapsed
US
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Synchronous DRAM having initial mode setting circuit
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1994-09-19
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Granted: 1995-09-05
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Expires: 2014-09-19
Abstract
Abstract The initial mode setting circuit 30 has a circuit 31 for generating a reset pulse RST after detecting that the power source voltage VCC has reached a specified value when the power source voltage VCC starts up, and fuses 32 to 37, each one end of which is commonly connected to the output end of the reset signal generating circuit 31 and the other ends of which are connected to one of either the set input end S or the reset input end R of the flip flops 11 to 13. The fuses 32 to 37 are melted and cut off electrically or with a laser.
Inventors
- 👤 Eiichi Nagai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:33
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/00; G11C7/10; G11C7/1015; G11C7/1045; G11C7/1072
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
118 words
A synchronous DRAM performing data input or output operation synchronized with a clock input in one of operating modes, the mode being set in a mode register, comprising: a command decoder for decoding a control signal from outside to generate a mode register setting signal and for, when said mode register setting signal is active, decoding a memory address to set the operating mode in the mode register; and an initial mode setting circuit for generating a reset signal after detecting that a power source voltage has reached a value after start up of said power source voltage and for setting an initial value of the operating mode in said mode register with timing of said reset signal.
Claim 2
Dependent Claim
118 words
A synchronous DRAM performing data input or output operation synchronized with a clock input in one of operating modes, the mode being set in a mode register, comprising: a command decoder for decoding a control signal from outside to generate a mode register setting signal and for, when said mode register setting signal is active, decoding a memory address to set the operating mode in the mode register; and an initial mode setting circuit for generating a reset signal after detecting that a power source voltage has reached a value after start up of said power source voltage and for setting an initial value of the operating mode in said mode register with timing of said reset signal.
Claim 3
Dependent Claim
121 words
A synchronous DRAM according to claim 1: wherein said mode register has flip flops, each of said flip flops has a set input end and a reset input end; wherein said initial mode setting circuit comprises; a reset signal generating circuit for generating a reset pulse from an output end after detecting that said power source voltage has reached a value when said power source voltage starts up; and non-volatile switching elements, one end of each of which being commonly connected to said output end of said reset signal generating circuit and another end of each of which being connected to one of either said set input end or said reset input end of one or more of said flip flops.
Claim 4
Dependent Claim
28 words
A synchronous DRAM according to claim 2 wherein said on-volatile switching elements are fuses cut off or not in accordance with said initial value of the operating mode.
Claim 5
Dependent Claim
59 words
A synchronous DRAM according to claim 2 wherein said non-volatile switching elements are wiring patterns having connection/disconnection between said output end of said reset signal generating circuit and said one of either said set input end or said reset input end of one or more of said flip flops in accordance with said initial value of the operating mode.
Claim 6
Dependent Claim
64 words
A synchronous DRAM according to claim 2: wherein said flip flops are N number; and wherein said non-volatile switching elements are 2N number, one end of each of which being commonly connected to said output end of said reset signal generating circuit and other ends of which being connected to said set input ends or said reset input ends of said flip flops respectively.
Claim 7
Dependent Claim
28 words
A synchronous DRAM according to claim 5, wherein said non-volatile switching elements are fuses cut off or not in accordance with said initial value of the operating mode.
Claim 8
Dependent Claim
59 words
A synchronous DRAM according to claim 5 wherein said non-volatile switching elements are wiring patterns having connection/disconnection between said output end of said reset signal generating circuit and said one of either said set input end or said reset input end of one or more of said flip flops in accordance with said initial value of the operating mode.
References Cited (Backward Citations)
US5311483A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |